Loads two double-precision values into floating-point registers and updates the address base.
Note: The lfqu instruction is supported only in the POWER2 implementation of the POWER architecture.
The lfqu instruction loads the two doublewords from the location in memory specified by the effective address (EA) into two floating-point registers (FPR).
DS is sign-extended to 30 bits and concatenated on the right with b'00' to form the offset value. If general-purpose register GPR RA is 0, the offset value is the EA. If GPR RA is not 0, the offset value is added to GPR RA to generate the EA. The doubleword at the EA is loaded into FPR FRT. If FRT is 31, the doubleword at EA+8 is loaded into FPR 0; otherwise, it is loaded into FRT+1.
If GPR RA is not 0, the EA is placed into GPR RA.
The lfqu instruction has one syntax form and does not affect the Floating-Point Status and Control Register or Condition Register Field 0.
|FRT||Specifies the first of two target floating-point register.|
|DS||Specifies a 14-bit field used as an immediate value for the EA calculation.|
|RA||Specifies one source general-purpose register for EA calculation and the target register for the EA update.|
The following code calculates the sum of six double-precision floating-point values that are located in consecutive doublewords in memory:
# Assume GPR 3 contains the address of the first # floating-point value. # Assume GPR 4 contains the address of the target location. lfq 7,0(3) # Load first two values into FPRs 7 and # 8. lfqu 9,16(3) # Load next two values into FPRs 9 and 10 # and update base address in GPR 3. fadd 6,7,8 # Add first two values. lfq 7,16(3) # Load next two values into FPRs 7 and 8. fadd 6,6,9 # Add third value. fadd 6,6,10 # Add fourth value. fadd 6,6,7 # Add fifth value. fadd 6,6,8 # Add sixth value. stfqx 7,0,4 # Store the two doublewords at the new # location.
Floating-Point Load and Store Instructions.