[ Previous | Next | Contents | Home | Search ]
AIX Version 4.3 Assembler Language Reference

divdu (Divide Double Word Unsigned) Instruction


Divide the contents of a general purpose register by the contents of a general purpose register, storing the result into a general purpose register.


divdu RT, RA, RB (OE=0 Rc=0)
divdu. RT, RA, RB (OE=0 Rc=1)
divduo RT, RA, RB (OE=1 Rc=0)
divduo. RT, RA, RB (OE=1 Rc=1)


The 64-bit dividend is the contents of RA. The 64-bit divisor is the contents of RB. The 64- bit quotient is placed into RT. The remainder is not supplied as a result.

Both the operands and the quotient are interpreted as unsigned integers, except that if the record bit (Rc) is set to 1 the first three bits of the condition register 0 (CR0) field are set by signed comparison of the result to zero. The quotient is the unique unsigned integer that satisfies the equation: dividend = (quotient * divisor) + r, where 0 <= r < divisor.

If an attempt is made to perform the division (anything) / 0 the contents of RT are undefined, as are the contents of the LT, GT, and EQ bits of the CR0 field (if Rc = 1). In this case, if the overflow enable bit (OE) = 1 then the overflow bit (OV) is set.

The 64-bit unsigned remainder of dividing (RA) by (RB) can be computed as follows:

divdu RT,RA,RB # RT = quotient
mulld RT,RT,RB # RT = quotient * divisor
subf RT,RT,RA # RT = remainder

Other registers altered:


RT Specifies target general-purpose register for the result of the computation.
RA Specifies source general-purpose register for the dividend.
RB Specifies source general-purpose register for the divisor.


This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

[ Previous | Next | Contents | Home | Search ]