I always wanted to know more ... read
introduction
2 7 Y E A R S O F I B M R I S C
1965 IBM ACS
In the 1960's IBM was behind in the scientific area and
wanted to design an advanced machine better than the CDC 6800, later called the
CDC 7600.
The idea for the ACS (IBM Advanced Computing Systems) design started in 1965 with John Cocke's vision of a scientific
supercomputer. This was several years earlier than the RISC work at Berkeley and
Stanford Universities. The ACS project (which evolved from "Project Y", that
started late 1963) was cancelled in 1968.
Many of the innovative CPU organization techniques pioneered in ACS were used in the IBM
RS/6000.
After ACS, John Cocke carried this understanding of compilers and instruction sets
with him to the IBM 801 project. John also greatly influenced the IBM Cheetah and
America projects, which were the predecessors to the RS/6000.
Links:
A
Secret 1960's Supercomputer Project
IBM’s ACS-1 Machine
Technical Description of IBM ACS Project |
|
 |
The
A.M. Turing Award
1987: John Cocke for significant
contributions in the design and theory of compilers, the architecture of
large systems and the development of reduced instruction set computers
(RISC); for discovering and systematizing many fundamental transformations
now used in optimizing compilers including reduction of operator strength,
elimination of common subexpressions, register allocation, constant
propagation, and dead code elimination. |
|
1974 the 801
IBM Reduced Instruction Set Computer
(RISC) technology
originated in 1974 in a project at the Thomas J. Watson Research Center to
design a large telephone-switching network. The computer needed was named the
801 (after Building 801, where the research was taking place).
The goal of the 801 was to execute one instruction per cycle. The experimental
801 was never build, but
the design, mostly developed by IBM researcher John Cocke, seemed to be an good
basis for a general-purpose, high-performance miniprocessor.
Links:
The
evolution of RISC technology at IBM (PDF)
1985 America
Based on the experimental design of the
801 and ACS ideas the
development laboratory in Austin completed a first prototype, where it
evolved into the superscalar (Instructions are handled paralel) RISC System/6000 (RS/6000) processor that was introduced into the market in
1990. Development work had been done under code name
"America" for the RISC chip research, and "RIOS" for systems
using the America technology.
1986 RT PC
The IBM RT PC is IBM's first RISC based UNIX
(Advanced Interactive Executive [AIX]) computer with 32 bits ROMP processor (without
floating point capability ...) that was first announced by IBM in January
1986. The IBM RT has had a varied life from its initial announcement. The RT was
considered as "not enough power, too high a price,
and too late" and thought to be part of IBM's Personal Computer
line ... (hence RT PC, later renamed to RT).
Links:
6150 RT PC Models 020, 025, and A25 IBM 6151 RT PC model 010
FAQ for AIX V2.2.1 on IBM RT systems 1
2 3 4
1986 Advanced Interactive Executive
AIX for the RT PC is announced.
The RT used the Virtual Resource Manager (VRM) that provided a virtual machine environment for
the kernel, allowing more than one operating system to execute. AIX was based on INTERACTIVE Systems Corporation's
IN/ix (the first commercial Unix).
Links:
IBM
RT Personal Computer System Overview
The IBM RT PC Advanced Interactive Executive (AIX) Operating System
RT PC AIX and Virtual Resource Manager
RT PC AIX Version 2.1
1987 AIX (PS/2)
IBM will provide the PS/2 AIX Operating
System as a subset of the multiuser, multitasking, virtual memory AIX operating
system currently available on the IBM RT PC.
Links:
PS/2 AIX Statement of Direction
Availability
of PS/2 AIX delayed ...
1990 POWER
Februari 1990 IBM announces its new RISC-based computer line, the
RISC System/6000 (later named RS/6000, nowadays eServer pSeries), running AIX
Version 3. The architecture of the systems is given the name POWER (now commonly referred to as
POWER1), standing for Performance Optimization With Enhanced RISC. They where based on a multiple chip implementation of
the 32-bit POWER architecture. The models introduced included an 8 KB instruction cache
(I-cache) and either a 32 KB or 64 KB data cache (D-cache). They had a single
floating-point unit capable of issuing one compound floating-point multiply-add
(FMA) operation each cycle, with a latency of only two cycles and optimized 3-D graphics
capabilities.
The model 7013-540
(30 MHz) processed 30 million instructions per
second.
Its electronic logic circuitry had up to 800,000 transistors per silicon chip.
The maximum memory
size was 256 Mbytes and its internal disk storage capacity was 2.5 GBytes.
Links:
RISC
System/6000 POWERstation/POWERserver 320
RISC
System/6000 POWERstations/POWERservers 520 AND 530
RISC System/6000 POWERserver 540
RISC System/6000 POWERstation 730
RISC System/6000 POWERserver 930
AIX Version 3
AIX Version 3 is announced.
Links:
AIX Version 3 (Februari, 1990)
Overview: IBM RISC System/6000 and related announcements
1991
With the alliance of Apple and Motorola, IBM started a plan for the future that would span a range from the small, battery-operated computer to very large supercomputers and
mainframes, resulting in the PowerPC family of microprocessors, a single-chip implementation for RISC-based hardware and software.
Links:
Understanding IBM pSeries Performance and Sizing
1992 RSC
January of 1992, the model 7011-220
(33 MHz) 
,
an entry-level desktop workstation, was announced, based on a single chip
implementation of the POWER architecture, usually referred to as RISC Single
Chip (RSC). I recall we used to say "the pizza box".
Links:
RISC
System/6000 POWERstation/POWERserver 220, 22W AND 22G
AIX PS/2 Version 1.3
Announcement of AIX PS/2 Operating System
Version 1.3 for IBM PS/2.
Links:
AIX
PS/2 Operating System V1.3 (September 1992)
Withdrawal:
IBM AIX PS/2 Operating System 1.3 (December 1994)
1993 SP
The IBM Scalable POWERparallel Systems (SP,
now commonly referred to as SP1)
offer a scalable platform for both serial and parallel applications. Based on
RISC System/6000 technology, the basic component of the in Februari 1993
announced 9076
SP1 is a system frame containing eight to 16 RISC System/6000 processor
nodes (max. four frames, 64 nodes).
The SP implements Massively Parallel Processing (MPP). All the processing nodes
have their own resources (processors, memory, disks and operating system): the
shared nothing architecture.
Links:
AIX
Parallel Environment
SP models 001, 002, 003, 004, A01, AND 101
More
SP models
2001 SP
Overview
PowerPC 601
The RISC System/6000 model 7011-250 (66 MHz) workstation, the first to be based on the
32-bit PowerPC 601
processor, was introduced in September 1993.
The 601 was the
first processor arising out of a partnership between IBM, Motorola, and Apple.
From IBM, the RISC Single Chip (RSC) microprocessor became the base design for
601. The superscalar machine organization of the 601 was improved to achieve greater
performance and additional custom circuit design was applied to reduce the die size
and to allow higher frequency operation. The Motorola 88110 microprocessor bus
interface formed the basis of the development of the 601 bus interface.
The 601 did not implement
the full PowerPC instruction set (some infrequently used instruction where
excluded) and some new instructions and features were added, such as support
for symmetric multiprocessor (SMP) systems. The 601 is capable of dispatching,
executing, and completing up to 3 instructions per cycle. Instructions issue to multiple execution
units (an integer unit, a
branch processing unit, and a floating-point unit), execute in parallel, and can complete out of
order.
An SMP has multiple processors that have their own cache, the memory and devices
are shared.
The 601 was a bridge from POWER to the full
PowerPC architecture, such as the 603,
604, and 604e.
Links:
POWERstation/POWERserver 250 Series
POWER2
The model 7013-590
(66 MHz) was announced in September 1993 and was the first RS/6000 based on the
32-bit POWER2
architecture. The
most significant improvement introduced with the POWER2 architecture for
scientific and technical applications is that the floating-point unit (FPU)
contains two 64-bit execution units, so that two floating-point multiply-add
instructions may be executed each cycle. A second fixed-point execution unit is
also provided. In addition, several new hardware instructions were introduced
with POWER2: quad-word storage instructions, hardware square root instruction
and floating-point to integer conversion instructions.
Initial models: 7013-58H (55 MHz),
7013-590 (66 MHz),
7015-990 (71.5 MHz).
Links:
POWER2
and PowerPC architecture
AIX Version 3.2.5
AIX V3.2.5 is announced: Maturity
(stability, quality).
Links:
AIX
Version 3.2.5 (September, 1993)
1994
Notebook
The RS/6000 7007-N40 (50 MHz) notebook workstation
(introduced in March) is the ideal portable companion for mobile professionals
who want to take AIX on the road. Based on the PowerPC 601.
Links:
7007-N40
IBM RS/6000 Model N40
SP2
The Scalable POWERparallel Systems 2 (SP2) was announced in April 1994. Based on IBM's
RISC System/6000 microprocessor technology and running AIX/6000 (as it was named
then), the SP2 could scale from
two to 128 nodes (processing elements). Using a POWER2 processor and other
options it performed twice
the processing power of the SP1 system.
Links:
Scalable
POWERparallel Systems 9076 SP2 and Enhancements for SP1
Scalable Parallel Computing
9076-xxx SP Family
AIX Version 4.1
AIX Version 4.1 is announced: Scalability (PowerPC support, 4-way SMP, Client/Server
pkg), new Standards compliance, Simplicity (graphical, fast installation, Common
Desktop Environment), HACMP Clustering.
Links:
AIX
Version 4.1 (July, 1994)
AIX
Version 4 Overview and Product Life Cycle Dates
AIX Version 4.2 Overview and Product Life Cycle Dates
AIX Version 4.3 Overview and Product Life Cycle Dates
1995 PowerPC 604
32-bit PowerPC
604 RISC System/6000 microprocessor (120
MHz) upgrade announced for the RISC System/6000 model 7020-40P
(66 MHz).
Links:
Motorola/IBM
PowerPC 604/604e
Windows NT PowerPC Edition
Announcement of Windows NT Workstation
3.51 for RS/6000 40P, 43P and with NT 4.0 (1996) other models.
Hmmm ... I'm not going to try it on my 43P ...
Windows
NT Workstation 3.51 Now Supports IBM Power Series
Windows NT Support for PowerPC Computers
1996 POWER2 Super Chip
October 1996 the
RS/6000 model 7013-595
(135 MHz) was announced with the new 32-bit POWER2 Super Chip (also known as P2SC). The P2SC is a single chip
implementation of the POWER2 eight-chip architecture, containing 15 million transistors on a single
chip using high-density CMOS-6S technology. It powered the wide and thin
nodes in SP systems.
Links:
SP
POWER2 Super Chip Nodes
RS/6000
In October (?) IBM renames RISC System/6000:
RS/6000.
PowerPC 603e
October 1996, announcement of the
portable workstation RS/6000
model 860 (166 MHz) - notebook - using the 32-bit PowerPC 603e processor.
PowerPC 604e
The
43P
models 140 and 240 with 32-bit
PowerPC
604e RS/6000 microprocessor (166 MHz)
are announced. The 604e is a superscalar processor capable of issuing four
instructions simultaneously. As many as seven instructions can finish execution
in parallel.
Links:
PowerPC
604e Technical Library
Windows NT for the PowerPC withdrawn
AIX Version 4.2
AIX Version 4.2 is announced: High-end scalability ( 8-way SMP, >2GB
memory), Standards: UNIX95 brand, RAS Enhancements, NFS V3.
Links:
AIX
Version 4.2 (April 23)
1997 RS64
The RS64 (also known as Apache) is the
first 64-bit PowerPC RISC processor (October
1997).
The RS64 is a superscalar processor optimized for commercial workloads. The processor has separate 64 KB L1 cache for instructions and
data and L2 cache controllers. The L2 caches run at full processor speed.
The RS64 contains a 16 byte interface to 2-way set associative 4MB L2 cache. The
RS64 is also used in the AS/400 (called A35). Predecessors of the A35, only
running OS/400 are the A10 (a.k.a. Cobra), the world's first 64-bit PowerPC
microprocessor, and A25 (a.k.a. Muskie).
IBM brings 64-bit technology to the market introducing the RS/6000 Enterprise
Server model 7017-S70
(125 MHz, code named Raven), the first 12-way SMP system, and AIX Version 4.3.
Links:
RS/6000
Enterprise Server Model S70 Blazes the 64-Bit Trail
AIX Version 4.3
AIX Version 4.3 is announced: Higher levels of
scalability (24-way SMP, 96 GB memory), 32/64-bit API support, UNIX98 
Branding,
Networking/Security (TCP/IP V6, IPsec), Web System Management, AIX
Workload Manager, Java JDT/JIT, 32-bit/64-bit
application coexistence and concurrent execution (the kernel is still 32 bits).
Links:
AIX
Version 4.3 (October 1997)
AIX
Version 4.3.1 (April 1998)
AIX
Version 4.3.2 (October 1998)
1998 RS64 II
PowerPC RS64 II 64-bit RISC microprocessor (also know as NorthStar) is the first
in the Star series processor family.
The in July 1998 announced RS64-II contains a dedicated 32 byte interface to a private 4-way set
associative 8MB L2 cache. The processor target operating frequency is 262 MHz.
The 262 MHz cards contain four processors per card. Up to three 4-way cards can
be installed in a RS/6000 7017-S70
to create a 4-way, 8-way, or 12-way system.
Links:
New Processors Enhance the IBM RS/6000 Model S70 Performance
POWER3
The new 64-bit POWER3 processor, announced October 1998, unifies the POWER2 architecture (P2SC) with the PowerPC
architecture, and was optimized for technical applications.
The SMP-capable POWER3 design
allows for concurrent operation of fixed-point instructions, load/store
instructions, branch instructions, and floating-point instructions. The POWER3
is capable of executing up to four floating-point operations per cycle (two
multiply-add instructions). Integer performance has been significantly enhanced over the
P2SC with the addition of dedicated integer and load/store execution units. The chip
features eight execution units fed by a 6.4 gigabyte-per-second memory
subsystem. The core includes two high-bandwidth buses: a 128-bit 6XX
architecture bus to main memory and 256-bit bus to the L2 cache that runs at
processor speed. The POWER3 also has on-chip 64KB data cache and a 32KB
instruction cache.
IBM's first 64-bit symmetric
multiprocessor (SMP) workstation is the POWER3 based RS/6000 43P 7043-260
(200 MHz).
Links:
RS/6000
43P 7043 Model 260
The
POWER3 Microarchitecture
Overview
of Recent Supercomputers
History
of POWER processors
Characterization of Web Server Workloads on Three Generations of IBM PowerPC
Microarchitectures (PDF)
1999
RS64 III
PowerPC RS64 III 64-bit
RISC microprocessor (also known as Pulsar) using copper technology. The RS64 III
microprocessor powers the in September 1999 announced RS/6000 model 7017-S80
(450 MHz). The frequency of 450 MHz was
accomplished by using IBM's new copper technology (CMOS 7S). The RS64 III has 8
MB of Level 2 (L2) cache per processor. The 6-way SMP can be expanded to a
24-way SMP and the system memory can be expanded to 96 GB.
Links:
Custom
circuit design as a driver of microprocessor performance
AIX Version 4.3.3
AIX Version 4.3.3 is announced.
links:
AIX
Version 4.3.x Overview and Product Life Cycle Dates
AIX
Version 4.3.3 UNIX Operating System ( September 1999)
2000 POWER3-II
 The
64-bit POWER3-II microprocessor design is based on IBM's
advanced CMOS 7S process, which is a re-implementation of POWER3
using copper interconnects.
New RS/6000 model 44P 7044-270
(375 MHz) using the 1-4 way SMP with POWER3-II copper-based
microprocessor.
The POWER3-III didn't surface, so POWER4 is the next ...
Links:
Power3-II
375/450 MHz Processors
RS/6000
44P 7044 Model 270
Why
copper?
Back
to the Future: Copper Comes of Age
|
|
| The
use copper "wiring" for integrated circuits in 1997 was a
breakthrough in semiconductor technology (smaller, faster, more
powerful and less costly). The first copper chip was a PowerPC for
Apple iMac systems (September 1998). |
 |
|
eServer pSeries
I
n October IBM renames RS/6000: eServer pSeries.
Links:
IBM
introduces servers for the next generation of e-business
A Server By Any Other
Name
RS64 IV
PowerPC RS64 IV 64-bit
RISC microprocessor (also known as Sstar) using copper and SOI technology.
The in October 2000 announced pSeries
680 (600 MHz) a is 6- to 24-way 64-bit SMP server with up to 96GB of system
memory and 16MB L2 cache for each 600 MHz processor.
Links:
A
multithreaded PowerPC processor for commercial servers
AIX 5L Version
5.0
The initial release of AIX 5L was not generally available. It was an Early
Adopter Release for OEM's and application developers to begin development of
true 64-bit applications for a 64-bit AIX kernel.
 |
Silicon-on-insulator (
SOI) technology improves
performance over bulk CMOS technology by up to 35% and reduces power requirements by up to
66%. SOI refers to placing
a thin layer of silicon on top of an
insulator such as silicon oxide or glass. The transistors would then be built on
top of this thin layer of SOI. The basic idea
is that the SOI layer will reduce the capacitance (the ability of a structure to
store electrical charge) of the switch, so it will operate faster.
SOI protects the millions transistors on a chip with a blanket of insulation,
reducing harmful electrical effects that consume energy and hinder performance.
The first SOI/copper-based chip was shipped in May 1999 (a PowerPC processor
used in new AS/400 models). |
2001 POWER4
 The POWER4 "Gigaprocessor" copper SOI 64-bit CMP microprocessor is based
on all earlier designs.
174-million-transistor POWER4 chip, with two 1.1/1.3 GHz five-issue superscalar
microprocessor cores, a triple-level cache hierarchy, up to 256 GB memory, a 10-Gbyte/s main-memory
interface, and a 45-Gbyte/s multiprocessor interface. The POWER4 is a CMP chip,
which means that it incorporates multiple processors on a single piece of
silicon.
AIX 4.3.3 is not supported on Power4.
Links:
IBM Journal of R & D - Vol. 46, No. 1, 2002 - IBM POWER4 System
pSeries 690 System Handbook
p690 --
a collection of white papers
p690
puts SPECjbb2000 leadership to rest
POWER4 System Microarchitecture
eSever
pSeries 690 Announcement
pSeries 690: Virtual Tour
IBM POWER4 microprocessor focuses on memory bandwidth
(PDF)
IBM
Project Regatta
Logical Partitioning (LPAR)
IBM Research
VLSI
Microprocessors
Linux
and AIX link up on IBM's biggest Unix server
Silicon-on-insulator (SOI) and Copper
Technology
VARBusiness:
IBM’s p690 Server: Less Is More |
 The in October
introduced 8- to 32-way 64 bit SMP server 7040-681
(type model, which is not logical ...) pSeries 690 (code-named
Regatta H) is the first server to use the POWER4 dual processor on a
chip, and is the first model
in the Regatta family). Advanced MultiChip Module (MCM) packaging
places up to eight POWER4 processors onto a package that fits in the
palm of a hand (8.5x8.5 cm).
This new class of pSeries is the first UNIX Datacenter system,
utilizing mainframe-inspired self management capabilities (eLiza).
Integrated static Logical Partitioning (LPAR)
support for up to 16 AIX 5L or Linux partitions. |
|
AIX 5L Version 5.1
AIX 5L Version 5.1 is announced in April: Higher
levels of scalability (POWER4 Support, 32-way SMP, 256GB memory, full 64bit
kernel and device drivers, Logical Partitioning), Advanced RAS, Networking
enhancements, Java 2 Version1.3, Linux Application Support (Linux affinity). AIX 5.1 also
supports 32-bit POWER architecture and Intel Itanium (on a limited basis)
architecture.
Links:
AIX 5L
AIX
5L Version 5.1
Monterey
- AIX on Itanium ?
Gartner assesses IBM's AIX 5L OS - Source:
ZDNet
SP2
Overview
The RS/6000 SP system hosts dozens to hundreds
of RISC processor nodes facilitating parallel processing capability.
The basic SP building block is the processor node. It consists of a POWER3
or PowerPC Symmetric Multiprocessors (SMP), memory, Peripheral Component
Interconnect (PCI) expansion slots for Input/Output (I/O) and
connectivity, and disk devices. Nodes have either a Symmetric
MultiProcessor (SMP) configuration (using PCI) or a uniprocessor
configuration (using MCA). The three types of nodes (thin, wide, and high)
may be mixed in a system and are housed in short or tall system frames.
Depending on the type of nodes used, an SP tall frame can contain up to 16
nodes and an SP short frame can contain up to 8 nodes. These frames can be
interconnected to form a system with up to 128 nodes (512 by special
order). Each node contains its own copy of the AIX operating system.
Links:
RS/6000
SP and Clustered IBM eServer pSeries Systems Handbook
RS/6000
SP Processors
Advanced Computer
Technology Center (ACTC)
RS/6000
SP Resource Center
RS/6000
SP Planning Volume 1, Hardware and Physical Environment |
 The
currently used 375 or 450 MHz POWER3 SMP nodes, are powered by the
64-bit 375 or 450 MHz POWER3-II microprocessor. Earlier nodes used POWER1 (62 MHz), POWER2
(66/77 MHz), PowerPC 604 (112/200/332 MHz), P2SC (120/135/160 MHz)
and POWER3 (200/222 MHz). |
|
2002 POWER4+
The POWER4+ processors (the name POWER4-II circulated before the announcement) are announced in November 2002.
Source: ComputerWire, 21/01/2002
Links:
IBM launches world's most powerful eight-way UNIX server and new POWER4+ processor
AIX 5L Version
5.2
AIX 5L Version 5.2 is announced in October:
Logical Partitioning (LPAR) Support
-
Dynamic LPAR adds or removes
processors, adapters and memory without requiring
a reboot
-
Dynamic reconfigurations APIs
permit middleware and applications to automatically
adjust to system resource changes
-
Dynamic Capacity Upgrade on
Demand (CUoD) permits activation of additional
processors without requiring a reboot
-
Dynamic Processor Sparing (with
CUoD) permits substitution of failed processors
with spare, unlicensed processors
Scalability, Capacity and Resource
Management
- 16MB Large Pages speed transfer of data from
storage to memory on POWER4™ enterprise
systems
-
Memory Affinity and Scheduling
Affinity localize workloads internally by utilizing
a subset of processors that share uniform access to a subset of system
memory on POWER4 enterprise systems
-
JFS2 file size and file system
support increased to 16TB and adds native file system
snapshot support
-
Enablement added for VERITAS
File System
-
Workload Manager module is
dynamic for the management of resources within
a partitioned or single-image system. Enhanced to offer time-based resource
policies and automatic administrator notification when resource limits
reached on "per class" basis. New resources managed include number
of processes, logins and connect time
Networking Performance and
Technology
Reliability, Availability
& Serviceability (RAS)
- System UE-Gard detects errors that formerly
would result in a checkstop and instead just terminates the affected thread
- Adds automatic "lost I/O" detection
and recovery
- Dynamic Processor Deallocation default is set
to "enabled"
- Enhanced diagnostics that identify adapter
cards and storage devices by physical
location
- Adds graphical trace log viewer
- Improved dump size estimation and scripting
for Automated Dump Analysis
- Added Multi-path I/O enablement for improved
connectivity and maintenance deferral
Security
- Adds Internet Key Exchange (IKE) support for
DHCP servers
- Adds Diffie-Hellman key agreement protocol
- Adds full Pluggable Authentication Module
(XSSO/PAM) support to help unify
different login mechanisms and reduce administrative overhead
- Adds authentication via x.509 certificates
- Adds IKE use of new, integrated random number
generator
- Kerberized r-commands are added to the
security services suite
- Adds enablement for Enterprise Identity
Mapping which is intended to associate the
identity of a user in one registry with the identity of the same user in
another registry
System Management
- Adds centralized management of groups of AIX
servers via Distributed Command Execution
Manager application
- Adds capability to manage Linux® operating
system-based Intel® servers along
with AIX-based POWER servers
- System tuning parameters are centralized in
SMIT and the Web-based System Manager
- Adds Linux client for Web-based System Manager
Interoperability
Base / Standards
- UNIX 98 Server certified
- Adds POSIX Asynchronous I/O support
- Adds DNS Bind Version 9 support for networking
- Adds LDAP client support for RFC 2307, IBM
Directory and custom schema for
networking
- SNMP protocol upgraded to Version 3
- Common Host Bus Adapter (HBA) API added to
improve storage interoperability and
management
- CIM management objects support added for
web-based system management
Tools for Performance, debugging and
transition
- AIX Toolbox for Linux Applications now
includes more than 380 applications
- Adds template-based AIX performance tuning via
a stanza based file that supports
persistent values and can be exported/imported to multiple servers
- Adds consolidated access to performance tuning
values in SMIT and Web-based System
Manager
- Adds xprofiler (GUI-based profiling tool) to
the base operating system
- Adds performance tools support for LPAR, Large
Pages and Memory Affinity
- Adds new thread analysis tools, curt and
splat, to the analysis tool suite
- Adds performance toolbox and iostat support
for ESS vpaths
- tprof tool is enhanced to provide multiple
process profiling, improved threads support
and support for emulation and alignment interrupts
- Kernel debugger is enhanced for crash and lldb
functions
- prtconf is enhanced to display processor speed
- Adds 14 new commands for /proc and 31
additional SVR4 commands
Links:
AIX Documentation Library
AIX
Documentation (PDF)
All AIX Commands (fast!)
AIX
V5.2 Release Notes
AIX
5L V5.2 Announcement
AIX Statement
of Direction (PDF)
Differences
Guide AIX 5.2
Installation
Guide AIX 5.2 (PDF)
Functional
Enh. Summary (PDF)
Functional
list of AIX commands
Product
Life Cycle Dates AIX 5.2
2003
POWER4+ Speeds Up
In May 2003 the pSeries 655 and pSeries 670/690 servers are upgraded with faster
POWER4+ processors. For the first time trial/temporary Capacity Upgrade on Demand
(CUoD)
is available in the pSeries (add processors and/or memory on-the-fly).
The original POWER4 chips were made using a 180 nanometer copper/SOI process.
The new dual-core POWER4+ chip is made using a 130 nanometer copper/SOI process
resulting in a higher clock speed and a generated heath reduction. The new
POWER4+ versions for the pSeries 670/690 machines will run at 1.5GHz and 1.7GHz.
The higher performance of the pSeries 670/690 is also due to the introduction of
a new optional RIO-2 (Remote I/O-2) backplane with support for 1GHz I/O busses
that support 133MHz PCI-X peripheral cards. This results in a aggregate I/O
bandwidth of 14 GB/sec for the pSeries 670 (was 6GB/sec) and 44 GB/sec for the
pSeries 690 (was 16GB/sec). The new memory cards of the pSeries 670/690 are
twice as dense as prior memory cards. Faster L3-cache runs at 567 MHz. The
pSeries 670 now supports up to 256GB of main memory and the pSeries 690 up to
512GB. RIO-2 is also available for the pSeries 650/655.
The 4-8 way pSeries 655 supports the 1.5GHz and the 1.7GHz POWER4+ chip and the
existing 1.1GHz and the 1.3GHz POWER4 chip. The machine starts shipping by the
end of May; upgrades start shipping end of July.
The 4-8-16 way pSeries 670 only supports the POWER4+ chip running at 1.5GHz and
the existing 1.1GHz POWER4 chip.
The 8-16-32 way pSeries 690 supports the 1.5GHz and the 1.7GHz POWER4+ chip and
the existing 1.1GHz and the 1.3GHz POWER4 chip. The pSeries 670/690 starts
shipping by the end of May; upgrades start shipping in August.
DLPAR has been improved to support 4 partitions on the pSeries 650/655 (was 2),
16 on the pSeries 670 (was 4) and 32 on the pSeries 690.
Links:
pSeries Announcement Brief
(PDF)
IBM introduces new high-end eServer systems fueled by POWER4+ processors
p690
Description
p670 Description
p655 Description
IBM pSeries and IBM RS/6000 Performance Report (PDF)
pSeries 670/690
with faster POWER4+ and double maximum Memory
pSeries 655
with faster POWER4+ and additional Memory Options
pSeries 650
with CUoD and faster Performance using RIO-2 Adapters
Capacity Upgrade on Demand
PowerPC 970
The BladeCenter JS20
with PowerPC 970 (PPC 970), 1.6 GHz processors is announced November
11,2003. IBM plans to support AIX in the third quarter of 2004.
The 64-bit PowerPC 970, a single-core version
of POWER4, can process 200 instructions at once at speeds of up to 2 GHz and
beyond while consuming just tens of watts of power. It is used in Apple
desktops, Apple Xserve servers, imaging applications, and -- increasingly -- in
networking applications.
Links:
BladeCenter
JS20 — Fast 1.6 GHz SMP processor brings POWER technology to the BladeCenter
environment
2004 POWER5
POWER5-based servers, which will support
64-way SMP and up to 512GB of main memory.
POWER5 (code-named Squadron) and POWER6 processors are planned to have an
ability called "Fast Path", that takes over tasks that software
currently handles more slowly. The acceleration feature will speed up several
communication tasks, including the TCP/IP processing used to read and write data
on the Internet, and the Message Passing Interface (MPI), used to harness
clusters of computers into a collective supercomputer. And the chip will
accelerate virtual memory subsystem, a frequently used operating system feature
that manages how higher-speed regular memory can be expanded by using slower but
bigger hard drives.
POWER5, which will be built initially with 130-nanometer (0.13 micron) features,
also will feature "simultaneous multithreading," a feature that allows
a single chip to act as two.
IBM plans to use POWER5 in "blade" servers as well, super-thin servers
stacked densely like books in a bookshelf. POWER4 produces 125 watts of power,
but a blade processor is constrained to about 25 to 40 watts.
"Partitioning," the ability to split a single big server into several
smaller ones, will improve. POWER4 permits a partition that's the size of a
single processor, but POWER5 will allow hundreds of partitions.
Ravi Arimilli (chief technology officer for IBM's Power line) stated in a recent
interview that IBM's coming POWER5 processor was "95 to 97 percent" of
the way toward a mainframe processor.
Source: eWeek, May 19, 2003
Source: CNET, 17/02/03
Source: The Register, 17/12/2002
Source: ComputerWire, 7/03/2002
Source: CNET, 25/04/2002
AIX 5L Version 5.3
AIX 5L Version 5.3 is expected somewhere around
August 2004.
Main features: sub-processor DLPARs (10 LPARs per processor), virtual IO,
intra-partition virtual ethernet, and shrink filesystem.
2005
2006 POWER6
Photos: Courtesy of International Business
Machines Corporation. Unauthorized use not permitted.