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AIX Version 4.3 Kernel and Subsystems Technical Reference, Volume 1

pci_cfgrw Kernel Service

Purpose

Reads and writes PCI bus slot configuration registers.

Syntax

#include <sys/mdio.h>
int pci_cfgrw(bid, md, write_flag)
int bid;
struct mdio *md;
int write_flag;

Description

The pci_cfgrw kernel service provides serialized access to the configuration registers for a PCI bus. To ensure data integrity in a multi-processor environment, a lock is required before accessing the configuration registers. Depending on the value of the write_flag parameter, a read or write to the configuration register is performed at offset md_addr for the device identified by md_sla.

The pci_cfgrw kernel service provides for kernel extensions the same services as the MIOPCFGET and MIOPCFPUT ioctls provides for applications. The pci_cfgrw kernel service can be called from either the process or the interrupt environment.

Parameters

bid Specifies the bus identifier.
md Specifies the address of the mdio structure. The mdio structure contains the following fields:
md_addr Starting offset of the configuration register to access (0 to 0xFF).
ms_data Pointer to the data buffer.
md_size Number of items of size specified by the md_incr parameter. The maximum size is 256 bytes.
md_incr Access types, MV_BYTE, MV_WORD, or MV_SHORT.
md_sla Device Number and Function Number.
(Device Number * 8) + Function.
write_flag Set to 1 for write and 0 for read.

Return Values

Returns 0 for successful completion.

ENOMEM Indicates no memory could be allocated.
EINVAL Indicated that the bus, device/function, or size is not valid.

Implementation Specifics

The pci_cfgrw kernel service is part of the Base Operating System (BOS) Runtime.

Related Information

Machine Device Driver in AIX Version 4.3 Technical Reference: Kernel and Subsystems Volume 2

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