HOW WAS THE SPEED OF THE NONBLOCKING CROSS-BAR

ITEM: RTA000052610



QUESTION:                                                                       
Our new SMP based systems include a nonblocking cross-bar switch.               
The IBM salesmanual states the switch is capable of 800 MB/sec                  
sustained and 1.8 GB/sec peak.  My customer wants to know under                 
what conditions this data was measured. What packet size did we use             
for this test?  Thanks.                                                         
                                                                                
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A: SMP systems.                                                                 
                                                                                
   The machine organization includes a data cross bar.  The memory              
   port is 288 bits wide (32 bytes) and can support 800 MB/sec.  The            
   data ports (one per pair of processors) are 72 bits wide (8 bytes)           
   and can provide 266.67 MB/sec.                                              
                                                                                
   So, the actual memory bandwidth available may be limited by either           
   the number of memory banks or number of processors.  Clearly, we             
   need four memory banks and four processors to sustain 800 MB/sec.            
                                                                                
   Addresses can be issued every three clock cycles and up to four              
   independent memory accesses can be in progress at any given time             
   (pipelined).  Memory READs may thus complete with three cycle                
   periodicity.  32 bytes is transferred from/to the crossbar for               
   every memory operation.  After any possible ECC correction, the              
   data is routed inside the crossbar to the appropriate processor port.        
   Processor ports are 72 bits wide (eight bytes) and four clock                
   cycles are used to transfer the 32 byte data block.  Thus, there             
   is ALWAYS a one cycle overlap within the crossbar whenever there             
   are two adjacent memory READs.  This provides an instantaneous              
   bandwidth of 1200 MB/sec, even though the actual delivery rate               
   from the memory is 800 MB/sec.  Additionally, there can be a cache           
   to cache transfer occurring between processors on the other two              
   data ports, so there may be another data transfer occurring on               
   the same physical cycle described above.  Thus, the peak                     
   instantaneous rate is 3x600 MB/sec (the peak transfer rates of               
   three crossbar ports).                                                       
                                                                                
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This item was created from library item Q676285      BBBJD                      
                                                                                
Additional search words:                                                        
BAR BBBJD CROSS HARDWARE IX JAN95 MEASURED NEW NONBLOCKING OZIBM               
OZNEW RATE RISCSYSTEM RISCSYSU SMP SPEED SWITCH SWITCHING SYS SYSTEM            
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WWQA: ITEM: RTA000052610 ITEM: RTA000052610
Dated: 10/1996 Category: RISCSYSU
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