QUESTION:
The announcement materials show the G30 as having the same bandwidth
to memory as the J30 and R30. Since the G30 is only a 2 to 4 way,
processors are added in pairs, and each processor pair only has a 64bit
bandwidth to memory, is the G30 bandwidth to memory 128 bit, or does
each processor have a 64 bit bandwidth to memory?
If I'm missing something in the internal CPU to memory communication
structure, any suggestions on reading materials would be appreciated.
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QUESTION:
What's the deal? It's in the announcement materials. Is it correct or
not? Fundamentally The J30/R30 are
CP0 CP1 CP2 CP3 CP4 CP5 CP6 CP7
| | | |
64+8bit 64+8bit 64+8bit 64+8bit
| | | |
256 bit aggregate to Memory
C R O S S B A R S W I T C H
The G30 must look like this....right?
CP0 CP1 CP2 CP3
| | | |
64+8bit 64+8bit 64+8bit 64+8bit
| | | |
256 bit aggregate to Memory
C R O S S B A R S W I T C H
Ken
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A: G30 bandwidth.
Since the G30 can only have 4 processors (two processor cards),
it's sustained data rate to memory is only 267MB/sec, with a
600MB/sec peak rate. This is because there are only two paths
from the Non-blocking Crossbar Switch to the CPUs as opposed to
the four paths available on the J30 and R30 (with a 800MBsec
sustained and a 1.2-1.4GB/sec peak).
Therefore, the diagram like this is correct:
CP0 CP1 CP2 CP3
| |
64+8ecc 64+8ecc
| |
C R O S S B A R S W I T C H
|
256+32ecc bit path to Memory
I received this information from an internal SMP class I attended
yesterday and today. I was unable to find any specific information
in the G30 publications (DRAFT) that stated this exactly.
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This item was created from library item Q676174 CWLBW
Additional search words:
ACC ACCESS BIT BUS CWLBW FULL G30 HARDWARE IX JAN95 J30 MAIN MEMORY
OZIBM OZNEW RISCSYSTEM RISCSYSU R30 STORAGE SYS SYSTEM UNIT 256
WWQA: ITEM: RTA000052507 ITEM: RTA000052507
Dated: 10/1996 Category: RISCSYSU
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