ITEM: CB2130L

RISCSYSU: Cache differnce between instruction, data, and L2 cache

Question: I have been asked to explain the differences between Data Cache,
          Instruction Cache, and L2 cache on a RS/6000. What are the
          differences.

Response:

After a program is loaded into main memory, the RS/6000 main processor
requests the very first instruction in the program. In compliance with
the request, the first instruction, along with the next several
instructions, is retrieved from the main memory and loaded into the
Instruction Cache Unit(ICU). It is used as a temporary holding area for
programming instructions that are likely to be next in line to be
executed.  When the main processor requests the next instruction, it
will first look in the ICU.  Most of the time, the next instruction
needed will already have been loaded into the ICU, eliminating the delay
associated with getting the instruction from slower main memory.

The primary functions of the ICU are:

     o  Fetch all instructions
     o  Execute branch and logic on Condition Registers instructions
     o  Dispatch instructions to the Fixed-Point Unit(FXU) and
        Floating-Point Unit(FPU)
     o  Process interrupts
     o  Maintain the architected Condition, Count, and Link registers
     o  Maintain interrupt control registers
     o  Provide engineering support processor (ESP) functions

The Data Cache Unit(DCU) is used to efficiently move the data on which
the programming instructions are to operate between the RS/6000 main
processor and main memory.  The DCU operates much like the ICU, only
the DCU provides temporary holding area for data needed during program
execution rather than programming instructions.  When a program
instruction requires data on which to operate, the DCU is first checked
to see if the needed data has already be loaded.  If the data is not
found (which is known as a cache miss) in the DCU, the needed data is
automatically loaded from the slower main memory to the DCU.

In general, the DCU provides an instruction reload buffer for
transferring instruction cache lines to the ICU, as well as store-back
buffers for data cache operations. The DCU also provides an I/O cache
for DMA operations.

The Level 2(L2) cache is a combined instruction and data cache. The L2
cache, typically much larger than the instruction and data cache,
reduces the effect of instruction or data cache misses by holding the
majority of code, which was initially loaded in the L2 cache from slower
main memory.  When instructions or data is not to be found in the ICU
or DCU, the processor first checks the L2 cache. If the data is not
found in the L2 cache, is loaded from the slower main into the L2
cache.

In conclusion, the different types of cache provide several temporary
holding areas for program data. The main processor fetches all
instructions and data from the ICU and DCU which together are some
times referred to as Level 1(L1)cache. The ICU and DCU fetch data from
L2 cache (when present, or from main memory when L2 cache is not
available), and L2 cache fetches data from main memory. L1 cache is
faster than L2 but smaller in size. L2 cache is typically much larger
than L1 cache but slower. Main memory is much slower than L2 cache.

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Support Line: RISCSYSU: Cache differnce between instruction, data, and L2 cache ITEM: CB2130L

Dated: September 1996 Category: N/A

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