ITEM: BE0942L
Having performance problems, payroll takes twice as long
Question:
Model r30
aix 4.1.4
Having performance problems
trying to run payroll
Response:
Env: AIX 4.1.4; RISC model R30
Desc: Have upgraded from a RISC 990 @ AIX 3.2 to a R30 @ 4.1.4 and
now thier payroll which runs on ORACLE is taking twice as long
to run. They also have a new version of ORACLE for AIX 4.1
installed.
Action: I asked Natasha how much RAM and paging space they have
installed/configured.
RAM = 1GB
Paging Space = 864MB
I recommended to Natasha that she increase her total paging
space to about 1.4Gb. I had her run vmstat, iostat, and ps
to check the system, everything else looked good. ORACLE
was the biggest processes running, but that is the only
application they really run on this system. The CPU showed
about %75 idle most of the time with only 1 job in the
run queue.
She has already contacted ORACLE about her problem and is
waiting to hear from them.
Next Action: Closing item with Natasha's consent.
Test Case: N/A.
Response:
Response:
Action:
Natasha had a question regarding the use of the 'nice' command.
Researched and called her back. She was not in, left message.
Response:
Response:
ACT: The system is really slow as per Natasha. Told her that I would
be paging somebody in the perf group to call her back. She would be
at the \# listed in the item. Kevin says he would handle it from here.
NEXT: rq to Kevin, thanks
Response:
ACT: Paged out to LXPERF. Got a call back from Russell S. of the performace
group. He will talk with Natasha about her problems and about some SMP
issues that he knows about.
NEXT: Over Russel S. queue.
Response:
E: 990 with 6 drives on 2 adapters; 12 serial drives on 1
r30 4 way with 32 ssa disks
A: Answered customer questions on checking system performance for
smp boxes versus single processor.
N: Requeuing to Russell.
Response:
Desc: I called Natasha back.
Action: I explained that since her payroll application is running
one just 1 of the processors then it will be slower on
the R30 than on the 990. The reson is that the R30 has
a 601 processor while the 990 has a Power 2. Here is the
break down:
Power 2 601
----------- ----------------
Handles 6 insturctions in pipe 3 instructions in pipe
2 fixed units 1 fixed unit
2 floating point units 1 floating point units.
The Power 2 chip is capable of doing twice the number
crunching than that of the 601 chip during the same
time period. Plus, there is a log of overhead maintaining
4 processors. For example, there is processor infinity which
invoked for each dispatch of a job to determine which processor
it would run best on. For a 4 CPU SMP box, processor
infinity will take 12 cycles to do its computation. Also,
with 4 CPU's sharing the same memory, a whole locking scheme
is used to prevent a processor from accessing a
location in memory while another CPU is changing that value.
This results in even more overhead.
Next Action: I am going to fax Natasha the above stats on the
different processors.
Response:
This is the informaiton I faxed Natasha:
The following outlines the characteristics of the Power2 chip and the
PowerPC Chip. The first big difference is that the Power2 chip on the 990
has a large amount of level 1 cache as comparied to the PowerPC chip
on a SMP box. It takes 1 clock cycle to access level 1 cache. Level 2 cache
takes 7 to 10 cycles to access! The other big difference is that a Power2
chip is capable of executing 6 instructions in one clock cycle, where as the
601 PowerPC chip can only handle at most 3 instructions per cycle.
Power2 Chip on 990
--------------------------
71.5 MHz
2 fixed-point units
2 floating-point units
Dual ported 256KB Level 1 data cache
32KB of Level 1 instruction cache
256-bit memory interface
higher performance branch processor
In a single clock cycle the Power2 chip can execute six instructions:
a branch instuction
two fixed-point instuctions
two floating-point instructions
and a Condition register logical instruction.
601 PowerPC Chip on a R30
---------------------------
75 MHz
1 fixed-point unit
1 floating-point unit
32KB on-chip Level 1 cache (instruction and data)
1 MB of Level 2 cache
256-bit memory interface
In a single clock cycle the PowerPC chip can execute three instructions.
SMP introduces the following overhead
--------------------------------------
Memory Locks - could cause processes to sleep until memory addresses are
unlocked. Prevents two processors from simutanously changing
a shared memory segment.
Processor Affinity - requires overhead to determine which processor a
thread should be dispatched to.
Response:
Closing with Customer Approval
Support Line: Having performance problems, payroll takes twice as long ITEM: BE0942L
Dated: May 1996 Category: N/A
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