Hardware Features

The Network Terminal Accelerator is a high-performance, Type 3 Micro Channel adapter. It handles all asynchronous terminal multiplexing for Ethernet transport media and TCP/IP emulation protocols.

The following figure represents the adapter card.

CPU

The adapter uses an Intel SuperScalar i960CA RISC-embedded processor that decodes and executes multiple instructions in parallel from a single instruction stream. At 25 MHz, using a conventional memory system and a burst bus only 32 bits wide, the adapter sustains an execution rate approaching 50 million instructions per second.

Coprocessor Support

The adapter includes a powerful combination of coprocessors:

• A 32-bit Intel 82596 LAN coprocessor to automatically handle Ethernet protocols
• An integrated interrupt controller
• A 1KB, two-way, set-associative instruction cache, eliminating bottlenecks by decoupling the instruction stream from the external bus
• A local register cache, dramatically reducing the number of memory accesses.

Local Memory

The memory architecture on the adapter features two-way bank interleaving, allowing optimized memory access. Memory is accessed in long-word (32-bit) increments. A two-bank interleaf scheme allows the access time of one bank to overlap the data time of the other, permitting the CPU to perform burst read cycles with one initial wait state, followed by zero wait states (1-0-0-0).

Two memory configurations are available on the adapter: the Network Terminal Accelerator-256 comes with 2MB, and the Network Terminal Accelerator-2048 with 8MB.

Micro Channel Interface

The adapter uses the Intel 82325 chip set designed by IBM. The 82325 supports:

• Address and data parity checking
• Burst mode data transfers
• Subsystem control block (SCB) registers
• Programmable DMA channel
• Internal error checking.