EXXX LCD Codes

E000-E00F SSC initialization
E010 Starting SP self-tests
E011 SP self-tests completed successfully
E012 Begin to set up SP's heap
E01F Bad self-test; can not continue...
E020 Configuring CMOS
E021 Configuring NVRAM
E030 Beginning to build I2C resources
E031 Finished building I2C resources
E032 JTAG self-test
E040 Starting Serial port tests
E041 Configuring a serial port (first time only)
E042 Configuring serial port 1
E043 Configuring serial port 2
E044 Preparing to set serial port line speed
E045 Preparing to disconnect serial port
E060 Preparing to auto power-on (AC restored)
E061 Preparing to auto power-on (Timer)
E070 Configuring modem
E072 Preparing to call home
E075 Entering SP menus

E076 Leaving SP menus; attempting to disconnect modems
E0A0 Beginning Bring-Up Phase
E0B0 Starting CPU BIST
E0BF CPU BIST fail
E0C0 Starting X5 (Cache controller) BIST
E0CF X5 (Cache controller) BIST fail
E0D0 Creating scanlog (takes a while)
E0E0 Pulling CPU(s) out of reset
E0E1 Pulling CPU out of reset: Passed
E0EF Pulling CPU out of reset: Failed
E0FF SP reports bad Service Processor firmware
E100 Reserved/Unused
E101 Video enabled, extended memory test (Quick restart path)
E102 Firmware restart with cfg'd parms (Quick restart path)
E103 Set memory refresh (composite img)
E104 Set memory refresh (recovery block)
E105 Transfer control to O.S. (normal boot)
E108 Run recovery block base memory (test 2k), set stack
E109 Copy CRC verification code to RAM
E10A Turn on cache
E10B Flush cache
E10C Jump to CRC verification code in RAM
E10D Compute composite image CRC
E10E Jump back to ROM
E10F Transfer control to Open Firmware
E110 Turn off cache, Check if composite image CRC is valid
E111 GOOD CRC - jump to composite image
E112 BAD CRC - initialize base memory, stack
E113 BAD CRC - copy uncompressed recovery block code to RAM
E114 BAD CRC - jump to code in RAM
E115 BAD CRC - turn on cache
E116 BAD CRC - copy recovery block data section to RAM
E117 BAD CRC - Invalidate and flush cache, set TOC
E118 BAD CRC - branch to high levelrecovery control routine
E119 Initialize base memory, stack
E11A Copy uncompressed recovery block code to RAM
E11B Jump to code in RAM
E11C Turn on cache
E11D Copy recovery block data section to RAM
E11E Invalidate and flush cache, set TOC
E11F Branch to high level control routine
E120 Initialize I/O and early memory block
E121 Initialize S.P.
E122 No memory detected (system lockup)
E123 No SIMM found in the socket
E124 Disable defective memory bank
E125 Clear PCI devices command reg, go forth
E126 Check valid image - start
E127 Check valid image- successful
E128 Disable interrupts, set int vectors for O.F.
E129 Validate target RAM address
E12A Copy ROM to RAM, flush cache
E12B Set MP operational parameters (eg. L.E.?, Real?)
E12C Set MP cpu node characteristics
E12D Park secondary processors in parking lot
E12E Primary processor sync
E12F Unexpected return from Open Firmware (system lockup)
E130 Build device tree
E131 Create ROOT node
E132 Create cpus node
E133 Create L2 Cache node
E134 Create memory node
E135 Create memory SIMM/DIMM node
E136 Test memory
E137 Create openprom node
E138 Create options node
E139 Create aliases node and system aliases
E13A Create packages node
E140 PReP style load
E149 Create boot mgr node
E14C Create terminal-emulator node
E14D Load boot image
E14E Create Client Interface node/dictionary
E14F NVRAM validation, config variable token generation
E150 Create host (primary) pci controller node
E151 Probe primary pci bus
E152 Probe for adapter FCODE, evaluate if present
E153 End adapter FCODE probe/evaluation
E154 Create pci bridge node
E155 Probe pci bridge secondary bus
E156 Create pci ethernet node
E15A Create 64 bit host (primary) pci controller node
E15B Transfer control to O.S. (Service mode boot)
E15C Probe primary 64 bit pci bus
E15D Create host pci controller node
E15E Create MPIC node
E15F Adapter VPD probe
E160 CPU Node VPD Creation
E161 ROOT Node VPD Creation
E162 SP Node VPD Creation
E164 Create pci graphics node (P9)
E168 Create pci graphics node (S3)
E16C GXT1000P Subsystem Open request
E16D GXT1000P Planar not detected/failed diagnostics
E16E GXT1000P Subsystem Open successful
E16F GXT1000P Close Subsystem
E170 Start of PCI Bus Probe
E171 Executing PCI-Delay function
E174 Establish host connection general information concerning network booting.
E175 BootP request general information concerning network booting.


E176 TFTP file transfer
E177 Transfer failure due to TFTP error condition
E178 Create pci token ring node
E180 SP Command setup
E183 SP Post
E190 Create isa node
E193 Initialize Super I/O
E196 Probe isa bus
E19B Create Service Processor node
E19C Create tablet node
E19D Create nvram node
E19E RTC node creation and initialization
E19F Create eeprom node
E1AD See description of checkpoint E1DE.
E1B0 Create lpt node
E1B1 Create serial node
E1B2 Create audio node
E1B3 Create 8042 node
E1B6 Probe for (ISA) keyboard
E1BA Enable L2 cache
E1BB Set cache parms for burst
E1BC Set cache parms for 512KB
E1BD Probe for (ISA) mouse
E1BE Create op-panel node
E1BF Create pwr-mgmt node
E1C0 Create isa ethernet node
E1C5 Create isa interrupt controller (pic) node
E1C6 Create dma node
E1D0 Create pci scsi node
E1D3 Create (* wildcard *) SCSI block device node (SD)
E1D4 Create (* wildcard *) SCSI byte device node (ST)
E1DB Create floppy controller (fdc)node
E1DC Dynamic console selection
E1DD Early processor exception
E1DE An alternating pattern of E1DE and E1AD is used to
indicate a "Default Catch" condition before the Open
Firmware "checkpoint" word (function) is available.
E1DF Create diskette drive (disk) node
E1E0 Program flash
E1E1 Flash update complete
E1E2 Initialize System I/O
E1E3 PReP boot image initialization
E1E4 Initialize Super I/O with default values
E1E5 XCOFF boot image initialization
E1E6 Set up early memory allocation heap
E1E7 PE boot image initialization
E1E8 Initialize primary diskette drive (polled mode)
E1E9 ELF boot image initialization
E1EA Load flash EPROM recovery image from diskette
E1EB Verify flash EPROM recovery image
E1EC Get recovery image entry point
E1ED Invalidate instruction cache
E1EE Jump to composite image
E1EF Erase flash
E1F0 Start O.B.E.
E1F1 Begin selftest sequence on boot device(s)
E1F2 Power On Password prompt
E1F3 Priviledged Access Password prompt
E1F5 Build boot device list
E1F6 Determine boot device sequence
E1F7 No boot image located
E1FB Scan SCSI bus for attached devices
E1FD Default Catch The operator panel will alternate between
the code "E1FD" and another "Exxx" code
where "Exxx" is the initialization point at
which the error occurred.

E201 Setup PHB BARC addresses
E202 Initialize PHB registers and PHB's PCI configuration registers
E203 Look for PCI to ISA bridge
E204 Setup ISA bridge PCI config. registers and initialize
E206 Look for PRISM on PCG and switch to 50MHz
E207 Setup Data gather mode and 64/32-bit mode on PCG
E208 Assign bus number on PCG
E209 Assign PCI I/O addresses on PCI
E20A Assign PCI I/O addresses on PCG
E20B Check MCERs stuck at fault
E20C Testing L2 cache
E211 IPL ROS CRC checking
E212 Processor POST
E213 Initial memory configuration
E214 Memory test
E216 Copy ROS into RAM. Setup Translation and C environment
E220 Final memory configuration
E299 Start C code execution.

E3xx Memory test
E440 Validate nvram, initialize partitions as needed
E441 Generate /options node nvram configuration variable properties
E442 Validate nvram partitions
E443 Generate nvram configuration variable dictionary words