P/390 hardware description

The single-slot PCI bus adapter card contains:

ESA/390 CMOS processor chip in the 5 MIPS range. The processor chip is a 0.6 micron CMOS gate array with 212K gates and 647 pins
Hardware floating point internal to processor
Loadable control store containing the horizontal microcode
32 or 128 MB S/390 memory
32-bit PCI interface

The I/O subsystem (channel, control units, and devices) is provided through emulation of selected IBM I/O devices using workstation resources. S/390 I/O performance increases with the speed of the workstation processor and disks.

The P/390 was designed and developed by IBM Fellow William F. Beausoleil and his group in Poughkeepsie, NY, USA. The P/390 established many firsts for CMOS design within IBM:

First to develop a single chip on CMOS 5X equivalent technology
First to develop a ESA/390 system with one fab pass
First to prove the value of hardware emulation and rapid prototyping
First to package 32 MB on a single board with .25Mil spacing

The P/390 allows mainframe-proven applications to run on a workstation class platform. This product was designed and qualified by IBM as meeting 100% of the ESA/390 Processor Architecture. Therefore, all S/390 programs, applications, and operating systems run on the P/390 without any modifications, reassembly, or conversion.

It is now possible to develop and test mainframe software at home or at work without burdening your corporate mainframe. Whether you provide S/390 solutions or are in need of a processor with a stable architecture for your solution, the P/390 may be the answer.