118 Error Code
H083955 118 ERRORS DURING POST ON 8590 AND 8595 SYSTEMS
The memory error logging process of the PS/2 8590 and 8595 systems:
During normal system operation, if a memory parity error occurs, the PS/2 8590 and 8595 system BIOS NMI (Non-Maskable Interrupt) handler captures and stores the location (A1, B1 etc.) of the SIMM being addressed when the failure occurred. This information is transferred from the hardware registers and logged into NVRAM . The system halts and a re-IPL is required.
Upon rebooting, a parity check entry in NVRAM is detected by POST, a 118 error is displayed and the reference partition is accessed. From here, three things can be done:
When the memory diagnostic is run, it moves the entry from NVRAM error log to a private error log (maintained by the diagnostic), allowing POST to once again run, without the 118 POST error.
It displays: "The Memory Module In Location XX Has Previously Been Found Defective. Has It Been Replaced?" (it is not displayed on a red screen due to a diagnostic limitation.)
This points to the memory module location that was being addressed when the parity error occurred (locates the failing SIMM).
This question is asked in order to determine when to erase the failing module location data. If a "YES" response is not entered, the question will be displayed every time the memory diagnostic is run, until a "YES" response is given.
A random memory parity error (caused by a noise spike, etc., as an isolated occurrence), does not necessarily mean that a SIMM is defective.
Highly intermittent memory errors (failure once a week, etc.) will probably log the same failing SIMM location consistently. A second error logged against a SIMM location will cause that SIMM to be de-allocated (by-passed) and the system will remain operational, if there is enough memory remaining to support the software involved. The exact amount of memory disabled depends upon several factors beyond the scope of this tip.
Replacement of a SIMM which is consistently identified as failing is recommended.
The following chart provides additional information useful in choosing the correct action to take in resolving memory parity and 118 POST error events.