Type 2 Complex
rf90952a  Reference Disk for Type 2
rd9095 Diagnostics for Type 2 (Common to T1-4)
192-100
IBM PS/2 486-25/50 Microprocessor Upgrade (CPU only!)
192-099 IBM PS/2 486DX2-50 Processor Upgrade

Type 2 BIOS Images

Specifications
      Memory supported, cache, features 
      Can I use a Kingston Turbochip?
        Running DX4-100 on L (Requires U23)
          U23 Position
          3172-002 "H" complex 93F1666  

      ODP vs. ODPR
         ODP in Original Socket
      Support for >1GB Disks as IML Drive 
      Overclock attempt
      Identify H and L Complexes
   Thinking of the Type Zero Complex (H complex close?)
      In Defense of the L
"H" / Upgrade 486SX 25 MHz  92F0079
 "L" / Upgrade 486DX2 50/25  92F0161   
   J1 Jumper 
"A" Complex (Japanese)
171 Post Errors on 8595 and 9595 systems
486SX-25 Diskette Data Loss ECA


"L" / Upgrade 486DX2 50/25  92F0161  "H" 92F0079 is similar...
U5 89F5724  Memory Controller 
U6 DMA Controller
U7 BIOS AM27C010-155
U8 486 Socket (5v)
U9 487 Socket H models only!
U10 64F8781 Memory Data Buffer 
U16 89F5415  MCA Buffer 
Y1 50 MHz Osc (half can or SMD)
U6 Variants
    Some Type-2 (92F0079) suffer from an "incompetent DMA-chip", which is P/N 92F1428 at position U6/GA-M on the card. Working Type-2s 92F0079 have a DMA-chip P/N 10G7808 at U6/GA-M. If U6/GA-M is 10G7808 a Turbochip should work fine. The earlier Type-2 use the 92F1428 -  which ends the experiment in odd results (permanent I9990044, 605 FDD errors, permanent 165 errors and inability to read from FDD).

U6 Variants
P/N 92F1428 (Bad)
P/N 10G7808 (Good)
P/N 10G4714 (Possibly Good)

J1 Jumper 

I just noticed J1 in April 2020. What is it for?

Type 2 BIOS Images

AM27C010-155DC 1 Megabit (131,072 x 8-Bit) CMOS EPROM

07G0463.BIN Original BIOS for earlier Hs - seen mostly with 92F1428 DMA Controller
41g9361.zip BIOS for all Ls and Hs. Came stock on Hs with 10G7808 DMA Controller



H with Rework 92F0079
U6 92F1428 U7 07G0463

  Resembles L.



Running DX4-100 on L (Requires U23)
Jay Bodkin said:
  I got a bizarre thing happening on my 8595 Type 2.  I upgraded the CPU from an Intel 486 DX2-50 to 486 DX4 -100. (I got the U6 P/N 10G4714).  The machine boots with the reference disk and it detects that the processor complex has changed.  The front panel has the usual code to go with that. Then it asks to perform automatic configuration, to which I replied y. Next, it complains that there are still unresolved configuration errors, and wants a reboot.  After another reboot the front panel displaying 9600-8N1 and refuses to boot further.

Peter Wendt replies:
  OK, so at least you're not in danger toasting the CPU. (Tastes pretty bad anyway - toasted or raw) FWIW: I ran the Kingston Turbochip-133 at 100MHz on various 25MHz Type-2 platforms, but all of them had the "competent" DMA chip 10G7808 at U6/GA-M *and* had the latest platform BIOS 41G9361.

Rear of H / L U23


All L complexi have U23.
Complex PCB is 06G6870, BIOS 07G0463, DMA 10G7808, sticker 48G8043
Complex PCB is 06G6870, BIOS 41G9361, DMA 10G4714, sticker 06G7009

H complexi with 48G8042 on sticker below CPU have U23
Complex PCB is 06G6870, BIOS 07G0463, DMA 10G7808

H complexi with 07G3152 on sticker below CPU do NOT have U23
Complex PCB is 06G4561, BIOS 07G0463, DMA 92F1428

   The presence of a Motorola XAA212 chip at position U23 (on the solder side of the board) seems also be a critical point: if it is there the board is made in 1992, earlier 1991-manufactured board lack this chip - and failed to work with anything faster than a DX2-25/50 (Or a DX2-33/66, which will run as a 25/50 there only anyway). DX4s or Evergreen, Kingston and such like based on a quad-clocked AMD 5x86 failed with no exception on the earlier ones.

   There should be a silk-screened "Date of MFG" number somewhere on the platform, like e.g. 2092A0700 - which means 20th week 1992 (first 4 digits). If yours is a 1991 platform or early 1992 without the U23 chip - forget about it. On these boards I had a failure-rate of 100% (about 20 out of 20 ...).

>Interestingly, putting back the 486 DX-2 50 doesn't work now either. It still gets stuck on the 96-8N1, even after removing the battery for a couple of minutes!

IBM wrote in the HMM "Remove the battery, then wait 5 minutes ..." (HMM, September 1993, P/N 71G9316, page 300, "96 8N1 Error Message") but empirical research showed that this doesn't work fairly often.

Shortening the battery connectors (with the battery removed of course) *and* toggling the startup password jumper seems to be the only fast cure. There seems to be a board logic, that ANDs the two conditions after a power-on and deletes the entire setup from the CMOS.

At least during the "hot phase" when the Mod. 90s and 95s can be found in larger amounts at the customers this procedure was the only one that worked in a sufficiently fast way. And I had quite a lot 95s under service ... ;-) (Some are mine now)

3172-002 93F1666

The 3172-002 uses a 95 single serial planar and an "H" complex with a 3172 flavor complex BIOS (93F1667). This particular 3172-002 complex is the later version with a 10G7808 DMA controller and U23 on the back. They will happily accept the 41g9361.zip BIOS .



Japanese Type A

Tatsuo Sunagawa sent this outline to me. Waiting on chip IDs, but this sort of reminds me of the L, where the complex was never meant to take an SX (which is my bet for the QFP). 66.66 MHz clock, is it a DX-33?



Complex BIOS Needed for >1GB IML
     Type 2 complexes require the combination of  BIOS 41G9361 and SCSI BIOS 92F2244/45 in order to handle IML drives >1GB (new limit is 3.94GB). The upgrade BIOS incorporates the 'Enhanced IML' which supports IML from a drive >1GB and "search IML" which allows IML from a drive other than ID6.    The SCSI BIOS 44/45 pair supports drives well over 8GB. Ed. You OS may have other ideas...
    The "old' complex ROMs' IML support somehow does not make (proper) use of "Enhanced IML", possibly due to bad bit-shifting and/or masking when 'translating' the 'cylinder, head, sector' information to and from the SCSI 'logical block/sector' value. 

Y1 Functions
   Swapping a 66.667Mhz osc in for the 50MHz one will result in a 00010200 code in the upper left hand of the screen and a system hang. The Y1 Oscillator drives both the data bus and the DMA controller. 0001 02XX ROM checksum or timer error.

ID H and L Complexes
   Both H and L have no L2 cache socket OR solder pads for one.

   H models (92F0079) came with a 486SX-25 in U8 and have a second socket (U9) for a 487 copro or a 486DX2-50 ODP upgrade chip. They will accept a Turbochip if the DMA controller is the good one.
   L models  (92F0161)came with a 486DX2-50 in U8 and have only solder pads at the U9 location. They will take a ODPR  or (with the good DMA controller) a Turbochip.

Thinking of the Type Zero Complex
The "low-end" 25 MHz 486 did not use a clock multiplier and is comparable to a 386/286 clock by clock.

Ed. So we have an "H" complex with a 486SX-25 (no L2 cache, and single path memory). It might be as close as you're gonna get to a Type Zero complex with a 386DX-20 (with or without L2 cache and 80385 L2 controller, and single path memory).


Specifications

Memory
Min/Max on system board: 8/64MB 
RAM: DRAM (PS/2 72-pin SIMM) 70ns parity checked (8 sockets) 
       The PS/2 486DX2-50 Processor Upgrade Option supports a maximum of 64MB of parity memory, 16MB of which are addressable by DMA.  The PS/2 486DX2-50 Processor Upgrade Option does not support 85ns memory SIMMs.

ROM: 128kb 
Cache: 8kb L1, 0kb L2 (no socket for cache)
Features
* No Level 2 cache socket on complex.
* H models socketed for a 487 copro or a 486DX2-50 MHz upgrade chip.
* High speed 25 MHz DMA - now synchronous with 486; 24 bit DMA.
* Faster bus arbitration (than Base 1) for better busmaster performance.
* Memory controller supports both interleaved (higher performance –pairs of SIMMs) and non-interleaved memory (allows single SIMMs). 
* 20 MB per second data transfer support (for MCA bus).

ODP vs. ODPR 
  The 169 pin is the ODP-version - substitutes a 487SX with the 486SX still in place. Important on  boards with soldered CPU or a second socket.
   The 168 pin is the ODPR-version, where the -R- stands for "Replace" ... it replaces the 486SX / 486DX respectively and does not need the "SX-disable" pin therefore. 

ODP in Original Socket
> > Dr. Jim, can the 169th pin be bent/removed and the CPU used?

> Yep.  The socket I just put into my P75 has an empty hole to allow that extra pin to pass.  I've drilled similar holes in older 486 sockets myself.  Carefully.  BTW, I've been informed that it is NOT the SX disable pin, just a key pin.  The SX disable is elsewhere.

 Jose Duran
   You are right, this pin is only a key pin without any signal. The SX disable pin is B14 (as far as I remember). I have installed an AMD DX5  on an upgrade socket with a voltage adapter. Since my cpu didn't have any SX disable signal on it. I had to solder a wire from pin B14 to ground, thus putting the SX into tristate. It works perfectly.



I Speak for the Humble L!
Actually Tony Ingenoso said
   Austin DID do some LAN server performance modeling along these lines and determined that there WAS a gain to be had from a dual 386 machine as a 386 file server could become CPU bound.  Once a 486DX-33 was fitted, even the heaviest traffic hitting the server wasn't enough to saturate the DX33 in a pure file server role.
    My own casual observations of the lowly (and IMO brilliant) DX2-50 T2 complex  validated Austin's results.  With all NT4 Server's performance monitoring turned on I was never unable to saturate the stock CPU on a 9595-0LF in a pure file server role.  It might run up to 80%, maybe even peak to 90%, but it never became saturated at 100%.  This was with several other PC hammering it over a 16mb T/R LAN.  Operating within its design purpose, doing what it was sold to do -- a stock T2 was is a word "sufficient" to the task in all respects, and remains so even today when run in a pure file server role.
    The problem is that TODAY, we are asking these machines to take on more than they were  intended to do initially.  Modern "desktop" usage has a dramatically different use profile than pure file servers have, and it shows.  GUI's are a big drag on performance, and the 95's placement of the video on the bus hurts quite a bit as well.

171 Post Errors on 8595 and 9595 systems
   Symptom: A 00017100 (171) error occurs on POST (Power-On System Test). This problem may occur on 8595/9595 models xLx or xHx systems during the installation of a LANStreamer MC32, MC16 or EtherStreamer MC32 in slot 8.
    Fix: Do not install any of the above referenced adapters in slot 8. Relocate the adapter to one of the other Micro Channel slots. No further engineering action is planned.

ECA100 - 8590/95, 486SX-25MHZ DISKETTE DATA LOSS
   This problem may allow bad data to be read from or written to a device WITHOUT any error indications or other evidence of system failure. This affects any device attached to the floppy controller that is "seen" as a floppy drive, such as some tape backup devices.

AFFECTED SYSTEMS:
   All systems using the 486SX/25MHZ complex FRU P/N92F0079. 

 NOTES:
 The following are no longer supported: 5.25" Diskette Adapter/A (6451007), 4869-001 360KB and 4869-002 1.2MB External Floppy. These adapters use a separate device driver (not BIOS), and DMA verify. Updating the system partition will NOT cure the problem.

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