RS/6000 MCA Systems with CPU Cards
20181115 - This list is neither complete or totally correct. The P/N are from the 2004 version of RSinfo. The 7012-Gxx units are confusing, as are the 7015-Rxx units. I have two sources, and they don't always match when they identify planar-mount or CPU board...
I would not assume CPU cards with the same CPU are identical, unless P/Ns match.
As always, contact ME with corrections or additions.
RS6000_CPU_Cards_List_01 this table in Word 2003 format. RTF available on request.
FRU CPU Speed
E1D PowerPC 601 75
C1D PowerPC 601 75
C4D PowerPC 604 112
E4D PowerPC 604 112
X4D PowerPC 604e 200
7015-R50 X4D 200 604e FRU / P/N
FRU MFG P/N
41L6222 <- 41L6221
41L5020 <- 41L5019
94H1087 <- 08L0375
08L0784 <- 08L0783
08L0373 <- 08L0372
07L8979 <- 07L8978
07L9397 <- 07L9398
94H0389 <- 93H9536
94H0389 <- 93H9535
94H0389 <- 93H9534
94H0389 <- 93H7201
The IBM RISC System/6000 processor: Hardware Overview
by H. B. Bakoglu, G. F. Grohoski, R. K. Montoye
Machine Organization of the IBM RISC System/6000 Processor
by G. F. Grohoski
FP - Floating Point Unit (FPU)
FX - Fixed Point Unit (FXU)
D - Data Cache Unit (DCU)
I - Instruction Cache Unit (ICU)
S - Storage Control Unit (SCU)
C - Input / Output Unit (IOU)
CLK - Clock
TCW - Translation Control Words (TCW) buffer
OCS - On-Card Sequencer (OCS)
Storage Control Unit (SCU)
The SCU is the central system controller . All of the communication between CPU (ICU, FXU, DCU), main memory, and I/O is arbitrated by the SCU. The CPU sends I-cache reload, D-cache reload and D-cache storeback requests to the SCU over the PBUS, and the SCU generates the appropriate memory-control signals. The SCU is the bus master for the memory and SI0 buses. It controls the interface between D-cache and system memory, and oversees DMA operations between main memory and the I/O unit. The SCU provides a data path for I/O loads and stores between the CPU and I/O unit via the PBUS and SI0 bus. The SCU also forms an interface to the IPL ROS. Memory scrubbing is
controlled by the SCU, and memory errors detected by the DCU are recorded by the SCU. The SCU contains the bank configuration registers, which indictate the size and starting point of each bank of storage in system memory.
Cost-Reduced CPU (RIOS .9 / 8 Chip)
One of the goals of this design was to use a common chip set to produce a family of processors with varying cost and performance. This was accomplished by designing the FXU, DCU, and SCU in such a way that they can operate with two DCUs as well as with four. This system configuration is illustrated in Figure 4. Because the chips are common to the two versions, they can be sorted so that faster chips are used in the high end and slower ones in the entry-level configurations. In this way, sorting for high speed is achieved without sacrificing the overall yield.
This configuration has a lower cost for two reasons. First, it has only two data-cache chips rather than four. Second, it requires a minimum of one memory card rather than two. (This is because two DCU in the cost reduced CPU have a two-word memory interface
compared to four DCUs in the full CPU, which have a four-word interface. Consequently, some of the bit-scattering features described for the full-size CPU do not apply to the cost-reduced CPU.) To accommodate the smaller cache size and narrower memory bus width, the D-cache line size is reduced to 64 bytes. In the cost reduced CPU, fixed- and floating-point data buses are dotted together. In addition, the DCU sends the data to reload the I-cache over the SIO bus rather than having a dedicated I-cache reload bs to the ICU.