Back to 6152 Academic System
System was housed in a Model 60, 1MB standard on the 6152 planar.
6152 "Crossbow" Adapter
Base images courtesy of William R. Walsh.
Y2 is probably the
MCA bus oscillator
6152 Memory Daughter Card
There are three different memory sizes available, 2, 4, and 8MB. From this, I posit that the Crossbow supports 256K, 512K, and 1MB 30 pin SIMMs. Further, note there are five SIMMs per bank. I believe that one SIMM per bank provides ECC, like that on the 7568 Gearbox systems.
SIMMs in the great William R. Walsh psychadelic retro
machine were TI
TM4256OU-12L with 9x TMS4256FML -12 chips per SIMM.
Multiple 6152 CPU Cards
|> In comp.sys.ibm.pc.rt article <Ffirstname.lastname@example.org>, email@example.com (Dan &) wrote:
|> :The Dec. '88 Release of AOS 4.3 supports 2 CPUs in and RT 6152. I do not know if IBM every released any instructions although I vaguely remember seeing them drift by some where. If memory serves, one also needs a modified version of the 6152 configuration diskette (the one with the diagnostics) so the bus addresses of the second CPU card can be set. One CPU could be used to run the X server leaving the other for more useful computations.
| Is there any other configuration possible? I'm somewhat more interested in distributed computing applications, and doubling your processing power is always nice. :-)
Please note that the multiple cpu stuff is completely UNSUPPORTED by IBM - it was a personal project that was sufficently far advanced to get code into the product but was much too late for the documentation and testing required for a supported feature. This feature is not exactly secret as it was demo'ed at the fall 1988 COMDEX as a technology demo with the two Risc bus masters running BSD 4.3 on top of OS/2 (sigh).
There is also a paper that I'm going to present at the IBM internal Unix conference next week, as it is not IBM CONFIDENTIAL I hope that I can also post that here as well. In any case, if anybody goes attempt to get a multiple-cpu system going please send me email with the results.
In any case here are some notes on how it is implemented followed by the instructions for how one builds a multi-cpu IBM 6152 system. Enjoy! Again - this is NOT a suported feature - use at your own risk etc. etc.
Multiple CPU Architecture for
DOS implementation details
OS/2 implementation details
Instructions on how to build a
AdapterName "RISC coprocessor card"
NamedItem Prompt "I/O port"
- install additional processor card, and use the
to autoconfigure the system. If the two processors have
of memory the first one (port 0x1e0) should have the
larger amount of memory,
as that is where one usually runs the X server.
For simplicity I will assume that each disk has the normal root, swap, and /usr partitions.
- create two new host names, e.g. if the original
system was 'frodo'
then create frodo-mc0, and frodo-mc1. frodo-mc0 will be
the gateway machine
for cpu1 to the rest of the world. (You should use your
local naming conventions
if they are different from what we use).
- change /etc/rc.config on hd1 to reflect the new hostname and network address, e.g. change network and hostname entries to:
- on the hd0 disk, add the following lines to rc.config, so that we make frodo into a gateway (this may require allocating a new network number for 'frodo')
- now you can boot
up the system.
Note that when unix.exe starts it will tell you that you
have 2 processors.
The first processor should now be able to come up
normally. Once it gets
to the login state you can hot-key to the second
and boot it. It should come up on the second disk by
default (e.g. boot
- if one wants to reboot the second cpu, one can do so by first halting or rebooting it (e.g. /etc/halt or /etc/reboot), and then issing the following commands (on cpu 0):
(note that you must put the 6152 version of boot into /boot rather than the RT version).
- note that messages about the state of the second cpu are displayed on the console of the master cpu so that one can determine that has halted or attempted to reboot.
- note that if your configuration file doesn't have the line device mc0 at iocc0 csr 0xffffffff priority 13 then it will need to be added in order to send packets between the two Risc cpu's.