Dual Bus Memory
(also called Dual Path)
(also called Dual Path)
System Block Diagram of Dual Bus System
There are two paths to the memory through the memory controller:
• A path from the CPU
• A path from the Micro Channel.
So, the CPU does not have a dedicated path to memory, instead, it can share access to the memory with a Bus Master. If you think about it, having a dedicated path would mean adding another 32 lines to the complex interface.
Why is this limited to the CPU and Bus Masters? If an adapter is being run PIO, that means the CPU is a lot more involved with controlling that adapter. A bus master can execute it's own operations.
Dual Bus Operation
A bus from the CPU to the memory controller, and a bus from the Micro Channel to the memory controller allows the CPU to use the system memory, while at the same time a bus master can be using the Micro Channel. The net result of this is a significant increase in processing power, but this will not be seen if you are using single tasking software, or running only one task in a multitasking environment.
In the Model 90 and 95 XP 486 systems the memory controller alternates access to the system memory between the CPU and any bus master. This will happen even if the bus master is controlling the bus to the memory. This can be seen in Figure 20 in the interleaving of Micro Channel Data (MD) with CPU Data (CD) between the memory controller and the memory.
During the time that a bus master has control of the system, the CPU can access
the system memory. If a transfer is in process at the same instant that the CPU
wants to use the memory, the CPU will be held off until that one part of the
transfer has finished. It does not have to wait for the total transfer to have finished
as in previous PS/2 systems. The wait for memory access is now @ 300 - 500 ns compared with up to 7 microseconds in previous PS/2 systems.
Figure 21 on page 37 shows that the IBM PS/2 Model 90 and 95 XP 486 systems allow CPU cycles to overlap bus master cycles more than in previous systems. The CPU executes cycles even after a bus master starts executing cycles, but the PS/2 8570 hits a cycle that locks the CPU out much sooner than the IBM PS/2 Model 90 and 95 XP 486 systems.
• Bus masters have exclusive access to system memory when CPU is running from internal cache or optional external cache
• Bus masters and CPU memory accesses are mixed when they both need to
use system memory
• The CPU has exclusive use of system memory when a bus master is accessing I/O on system board or an adapter on the Micro Channel.
Note: The memory used in the IBM PS/2 Model 90 and 95 XP 486 systems is dual bus NOT dual-ported so the CPU may be held off for the current bus master transfer to complete, but not the full transfer.
Dual Bus Timing
Single Bus Operation
The bus master can hold the system bus, and as there is only one bus, it does not
matter to which part of the system the bus master is transferring data. The CPU
will have to wait, and arbitrate for control of the system bus, so that it can get to
the system memory. This was good for the bus masters, but not so good for the
CPU. When a bus master took control of the system bus, the processor had to wait for the bus master to release the bus, or had to arbitrate for control of the bus. This could take up to 7 microseconds.