DMA Controller SCB Interface
DMA Controller Architecture (Jul 1992) (pg 39-82)
    Type 1 and 2 Controllers with their features and programming.
     The original 1990-section covers only the base (Type 1) DMA controller.

SCB interface  

The SCB interface uses a form of the Locate mode described in the Subsystem Control Block (SCB)1 architecture. The system master uses the I/O registers to control the interface, report status, and enqueue control blocks; it uses the control blocks to manage DMA operations.

The control block specifies the type of operation, the source and destination addresses of the data, and other parameters. The source or destination addresses can point to a data location or to an indirect list that points to several locations. The width of each transfer can be 8, 16, 24, or 32 bits and is determined dynamically by the signal protocols used on the system channel.

All channels support 32-bit memory addressing, 32-bit transfer counts, and data chaining. Therefore, each operation can transfer an unlimited amount of data to any location within the memory address space from 0 through 4GB (2^32).

Each DMA channel has a local arbiter that can be programmed independently to request the system channel and arbitrate for a device.

The SCB architecture is an extension to the registers and operations of the PIO architecture.

1. *The SCB architecture is defined in the Personal Systems/2 Hardware Interface TechnicalReference—Architectures.

SCB Interface Registers  

The SCB interface registers control and monitor the state of the DMA controller and each DMA channel in the DMA controller. The registers can be divided into four functiona! categories: system interface, SCB control, operational control, and transfer control.

The following shows the registers and ports used by, and the I/O addresses associated with, the SCB interface. The page number indicate where the register is described.

Figure 10. I/O Addresses and Registers — SCB Interface
I/O Address;Register;R/W;Page Number
System Interface Registers;;;
0018;Function;R/W;35
0019;Extended Function;R/W;36
001A;Execute Function port;R/W;na
;Byte pointer;na;36
SCB Control Registers;;;
;Control Block Address;R/W;37
001C;Attention;W;38
001D;Subsystem Control;W;38
001F;Command Busy/Status;R;39
;indirect List Address;R;40
;indirect List Count;R;40
Operation Control Registers;;;
;Arbitration Level;R/W;41
;DMA Mask;R/W;42
;DMA Status;R;43
Transter Control Registers;;;
;DMA Mode R 44
;I/O-Memory Address;R;46
;Memory Address;R;47
;Transfer Count;R;47
;Data Holding;R;47

NOTE: Programs and hardware writing to reserved areas should ensure that the areas are set to 0 (unless otherwise indicated); programs and hardware reading these areas should treat them as don't care.

System interface Registers  

These registers control the overall interface to the DMA controller and each of the DMA channels. They are also used to report the status of each of the DMA operations.

Function Register  

The Function register is an 8-bit, read/write register that is used to select the DMA channel and specify the command to be performed.

This register is accessed using the Read or Write Function command (see page 62).

IMAGE Function Register [pg 41]

FUNC The Function field (bits 7-4) selects commands to be performed by the specified DMA channel. (For information on command selection, see “Commands” on page 61.)

SEL The Select field (bits 2-0) specifies the DMA channel that is to perform the command.

Extended Function Register  

The Extended Function register is an 8-bit, read/write register that is used to specify additional commands.

This register is accessed using the Read or Write Extended Function commands (see page 62).

IMAGE Extended Function Register [pg 42]

EFNC The Extended Function field (bits 7-0) defines additional commands to be performed. (For information on command selection, see “Commands” on page 61.)

Byte Pointer  
The byte pointer is a 2-bit, internal register that is used to point to the individual bytes in multiple-byte registers. The byte pointer is increased by 1 for each read or write operation to the Execute Function port (hex 001A).

The contents of the byte pointer cannot be accessed. The byte pointer is cleared (set to point to the first byte of a register) automatically after the Write Function and Write Extended Function commands (see page 62).

IMAGE  Byte Pointer [pg 42]

After the byte pointer is cleared, it points to bits 7-0 of a multiple-byte register. As each byte in the register is accessed, the byte pointer is increased to point to the next byte within the register. After the last byte (high byte) within the register is accessed, the byte pointer is undefined and must be cleared (set to point to the first byte).

SCB Control Registers  

These registers are used to enqueue and manage SCB-fetch operations (control block and indirect list).

Control-Block Address Registers  

There are eight Control-Block Address registers, one for each DMA channel. Each register is a 32-bit, read/write register that contains the address of the control block being queued.

The Control-Block Address register is accessed using the Read or Write Control-Block Address command (see page 72).

IMAGE Control Block Address [pg 43]

Attention Register  

The Attention register is an 8-bit, write-only register that is used to send an attention request to a DMA channel. The register is loaded using the Write Attention Code command (see page 75).

The Attention register is reset using the Reset DMA Controller and the Reset DMA Channel commands (see pages 64 and 64).

IMAGE Attention Register [pg 44]

ATTN The Attention field (bits 7-4) is used to initiate DMA operations using the SCB interface. The only request supported is the start control block request (hex 03), which causes the DMA controller to enqueue a request to start a control-block operation for the specified DMA channel.

SEL The Select field (bits 2—0) specifies the DMA channel that is to perform the request.

Subsystem Control Register  

The Subsystem Control register is an 8-bit, write-only register that provides global control of the SCB interface. The register is loaded using the Write Subsystem Control command (see page 75).

IMAGE Subsystem Control Register [pg 44]

RR The Reset Reject field (bit 5) restores the SCB interface to a state in which it can receive additional attention requests. When this field is set to a 1, the command-rejected condition is cleared, and the Busy and Reject fields are reset to 0. If the DMA controller is not in the command-rejected condition, setting this bit to 1 has no effect.

Command Busy/Status Register  

The Command Busy/Status register is an 8-bit, read-only register that contains the status of the control block operation.

The contents of this register is returned using the Read Command Busy/Status command (see page 75). The fields are cleared using the Write Subsystem Control command (see page 75).

All fields in the register are cleared (set to 0) following the Reset DMA Controller or Reset DMA Channel commands and following a hardware reset.

IMAGE CMD Busy/Status Register [pg 45]

REJ The Reject field (bit 4) indicates whether an error has been detected while processing a control block. When the field is 1, the DMA controller has detected an error while fetching or processing a control-block operation and the command is rejected. When the field is 0, the DMA controller did not detect an error.

An error condition also sets the Busy field to 1 (see “Error Processing” on page 59).

BSY The Busy field (bit 0) indicates whether the last write to the Attention register was processed. When the Attention register is loaded, the Busy field is set to 1. The DMA controller sets the field to 0 (not busy) after it has serviced the Attention register, making the register available to accept another request.

Programs must not write to the Attention register while either the Busy or the Reject fields are 1.

Indirect List Address Registers  

There are eight Indirect List Address registers, one for each DMA channel. Each register is a 32-bit, read-only register that points to the next entry in the indirect list. The register is used only during operations involving data chaining.

lf data chaining is being used, the Indirect List Address register is loaded with the contents of the Address 2 field when the control block is fetched. The register can be read using the Read Indirect List Address command (see page 73).

IMAGE Indirect List Address Register [pg 46]

Indirect List Count Registers  

There are eight Indirect List Count registers, one for each DMA channel. Each Indirect List Count register is a 32-bit, read-only register that contains the number of bytes remaining in the indirect list. The register is used only during operations involving data chaining.

if data chaining is being used, the Indirect List Count register is loaded with the contents of the Transfer Count field while fetching the control block, The register can be read using the Read Indirect List Count command (see page 74).

IMAGE Indirect List Count Register [pg 46]

Operation Control Registers  

These registers are used to control the operation of and maintain the status for each DMA channel.

Arbitration Level Registers  

There are eight Arbitration Level registers, one for each DMA channel. Each Arbitration Level register is an 8-bit, read/write register that contains the arbitration level assigned to the specific DMA channel.

The DMA controller compares the arbitration level used in winning control of the system channel to the value in each register. If the content of a register matches the winning arbitration level and DMA operations for that channel are enabled (not masked), the DMA controller starts the DMA operation.

The registers are accessed using the Read or Write Arbitration Level command (see page 68).

IMAGE Arbitration Level Register [pg 47]

ARBL The Arbitration Level field (bits 3-0) specifies the arbitration level for this DMA channel. An arbitration level of hex F is reserved for the default master, and the DMA controller does not respond to this level.

DMA Mask Register  

The DMA Mask register is an 8-bit, read/write register that contains one field for each DMA channel. The individual fields control whether DMA operations are enabied or disabled for that channel. If DMA operations are enabled for a DMA channel, the DMA controller enters the transfer state when it gains control of the system channel.

During normal operation, the DMA controller sets the Mask field to 0 when attention code 03 is written and sets the field to 1 when the DMA operation is completed.

The individual fields can also be set to 1 using the Set DMA Mask command, and set to 0 using the Reset DMA Mask command (see page 63). All mask fields are set to 1 after a DMA controller reset (see page 64).

The inverse of this register can be read using the Read DMA Busy command (see page 68).

IMAGE DMA Mask Register [pg 48]

M7-M0 The Mask fields (bits 7-0) are used to enable and disable DMA operations on each of the DMA channels. When a Mask field is set to 1, the mask is set and the channel is disabled. When a Mask field is set to 0, the mask is reset and the channel is enabled.

DMA Status Register  

The DMA Status register is a 16-bit, read-only register that contains the status for the eight DMA channels. The DMA Status register can be read using the Read DMA Status command (see page 67).

As each byte is read, its status is cleared (the byte is set to 00). Performing a Reset DMA Controller command clears the status in both bytes.

IMAGE DMA Status Register [pg 49]

TC7-0 The Terminal Count fields (bits 15-12 and 7-4) indicate whether the corresponding DMA channel has completed a DMA operation (transfer count has reached 0) since the status was previously cleared. lf the field is 1, the channel has completed a DMA operation: if the field is 0, the channel has not completed a DMA operation.

RQ7-0 The DMA Request fields (bits 11-8 and 3-0) indicate whether the corresponding DMA channel has transferred data since the status was previously cleared. If the field is 1, the channel has been active; if the field is 0, the channel has not been active.

Transfer Control Registers  

These registers determine the operation of the DMA channel and are used to control the source and destination addresses of each transfer and the number bytes transferred. During SCB-fetch operations, fields in the control block and indirect list are loaded into these registers. The registers are then used during the transfer.

DMA Mode Register  

There are eight DMA Mode registers, one register for each DMA channel. Each register is a 16-bit, read-only register that controls the operation of that DMA channel. This register is loaded with values that are based on the Command word read when the control block is fetched.

The register is read using the Read DMA Mode command (see page 68).

IMAGE DMA Mode Register [pg 50]

ARCH The Architected field (bit 15) is loaded from the Architected field of the Gommand word and is used to indicate whether the control block follows the format defined by the SCB architecture. The DMA controller uses a unique format and does not use the architected format.

This field must be set to 0 to indicate that the format of the control block is specific to the DMA controller.

RDC The Residual Data Control field (bits 13 and 12) is used to control operation of a Data Holding register if it is implemented as a FIFO buffer. If the Data Holding register is not implemented as a FIFO, the DMA controller sets this field to binary 00 (no residual data) during the SCB fetch operation.

This field is valid onty when the Extend Register field is set to 1. (For information on FIFO implementations, see Appendix 8B, “FIFO” on page 79.)

TC The Terminal Count field (bit 11) controls whether the DMA controller drives the ‘transfer count’ signal (Tc) active after it completes the transfer. This field is valid only when the Extend Register field is set to 1.

When the Terminal Count field is set to 1, the controller drives Tc active; when the field is set to 0, the controlier does not drive Tc active

EXT The Extend Register field (bit 7) determines whether bits 15-8 in the DMA Mode register are used. When the field is set to 1, the fields in the high byte are used. When the field is set to 0, the fields in the high byte are ignored, and the DMA controller operates as if the high byte is set to hex 08 (terminal count enabled).

This field is set to 1 by the DMA controiler during the SCB fetch operation.

S16 The Size 16 field (bit 6) to 0 by the DMA controller during the SCB fetch operation.

DEC2 The Decrement 2 field (bit 4) specifies whether the DMA controller increases or decreases the address in the Memory Address register. When the field is set to 1, the Memory Address register is decreased for each DMA transfer cycle. When the field is set to 0, the Memory Address register is increased.

XFER The Transfer Control field (bits 3 and 2) specifies the type of operation to be performed by the DMA channel.

Figure 11. DMA Operation Selection  
Transfer Control;Operation Performed
0 0;Memory verify
0 1;Memory-to-I/O transfer (memory is the source)
1 0;Memory verify
1 1;I/O-to-memory transfer (memory is the destination)

IOA The I/O Address field (bit 0) determines whether DMA controller uses the I/O address in the I/O-Memory Address register or I/O address hex 0000 during the DMA operation. When the field is 1, the DMA controller uses the address in the I/O-Memory Address register. When the field is 0, the DMA controller uses I/O address hex 0000 for the DMA transfer.

I/O-Memory Address Registers  

There are eight I/O-Memory Address registers, one for each DMA channel. Each register is a 32-bit, read-only register that contains a 16-bit I/O address, which remains unchanged throughout the DMA operation. The I/O address is defined by bits 15-0; bits 31-16 are reserved and forced to hex 00.

The I/O-Memory Address register is loaded with the Address 1 field when the control block is fetched from memory (see page 57). The register is read using the Read I/O-Memory Address command (see page 65).

IMAGE I/O Memory Address Register [pg 52]

Memory Address Registers  

There are eight Memory Address registers, one for each DMA channel. Each register is a 32-bit, read-only register that contains a memory address used during DMA transfers. The address is increased or decreased as data is transferred.

The Memory Address register is loaded with the content of the Address 2 field when fetching a control block or when fetching an entry from the indirect list.

The Memory Address register is read using the Read Memory Address command (see page 66).

IMAGE Memory Address Register [pg 53]

Transfer Count Registers  

There are eight Transfer Count registers, one for each DMA channel. Each register is a 32-bit, read-only register that contains the number of bytes to be transferred.

The Transfer Count register is loaded with the Transfer Count field when fetching a control block or when fetching an entry from the indirect list.

The Transfer Count register is read using the Read Transfer Count command (see page 67).

NOTE: A transfer count of 0 is not supported and causes a control-block error.

IMAGE Transfer Count Register [pg 53]

Data Holding Register  

The DMA controller uses the Data Holding register to temporarily store the data being transferred. The minimum size of the Data Holding register is 4 bytes and the maximum is 255 bytes.

Data Structures  

The DMA controller defines two control structures used by the SCB interface. Transfer control structures define the physical limits of the transfer. SCB control structures specify the format of the command blocks and indirect lists.

Transfer Structures  

There are two types of transfer-control structures defined: address and count.

Address  

The address structures are either memory or I/O addresses.

The memory address is a 32-bit, byte-aligned address. The entire memory address space (4GB), which is represented by the 32-bit address, is accessible through the SCB interface. The memory address is undefined when increased beyond hex 0FFFFFFFF or decreased below 0.

The I/O address is a 16-bit byte-aligned address.

Transfer Count  

The transfer count is a 32-bit value that specifies the exact number of bytes to be transferred. Unlike the transfer count in the PIO interface (which is zero-based), the transfer count is one-based, and the transfer is completed when the count reaches 0 for the last block to be transferred.

Control Structure  

The DMA controller implements a subset of the Locate mode from the Subsystem Control Block (SCB) architecture. The control block (the primary element) ts a 16-byte data structure that is set up in memory to define the parameters for the DMA operation and to point to the data areas to use in the operation. The control block must be aligned on a doubleword boundary.

These control blocks specify the source and destination addresses by pointing to the location to be used (nonchained) or by pointing to an indirect list that points to the location to be used (data-chaining).

All information pertaining to the DMA operation is contained in the control block and related data structures. The operation is completed when all data for a specified block has been transferred and no blocks remain to be transferred.

Figure 12. Control Block Structure  
15                 0
Command Word
Enable Word 1
Address 1 (low)
Address 1 (high)
Address 2 (low)
Address 2 (high)
Transfer Count (low)
Transfer Count (high)

Command Word  

The Command Word field is a 16-bit field that defines the parameters used in the DMA operation. Specific fields are loaded into the DMA Mode register during the fetch of the contro! block. (For definition of these fields, see “DMA Mode Register” on page 44.)

IMAGE Command Word [pg 55]

ARCH The Architected field (bit 15) is loaded into the Architected field of the DMA Mode register. This field must be set to 0 to indicate that the control block has a format that is unique to the DMA controller. If the field is set to 1, the DMA controller immediately returns an error indicating an unsupported control block.

RDC lf the Data Holding register is implemented as a FIFO buffer, this field (bits 13 and 12) is loaded into the Residual Data Control field of the DMA Mode register. Otherwise, the field in the DMA Mode register is set to binary 00.

TC The Terminal Count field (bit 11) is loaded into the Terminal Count field of the DMA Mode register.

DEC2 The Decrement 2 field (bit 4} is loaded into the Decrement 2 field of the DMA Mode register.

XFER The Transfer Control field (bits 3 and 2) is loaded into the Transfer Control field of the DMA Mode register.

IOA The I/O Address field (bit 0) is loaded into the I/O Address field of the DMA Mode register.

Enable Word 1  

The Enable Word 1 is a 16-bit field that defines additional parameters to be used with this control block.

IMAGE Enable Word 1 Register [pg 56]

IL1 The Indirect List 1 field (bit 12) specifies whether this control block uses data chaining or not. When the field is set to 1, data chaining is used, and the Address 2 field in the control block points to an indirect list, and the Transfer Count field specifies the number of bytes in the indirect list.

When the field is set to 0, the Address 2 field is a memory address to be used in the DMA operation and the Transfer Count field specifies the number of bytes to be transferred.

Address 1  

The Address 1 field is a 32-bit field that is loaded into the I/O-Memory Address register during the fetch of the control block.

IMAGE Address 1 Field [pg 57]

Address 2  

The Address 2 field is a 32-bit field that is loaded into the Memory Address register or the Indirect List Address register during the fetch of the control block. The register loaded is determined by the Indirect List 1 field in Enable Word 1.

IMAGE Address 2 Field [pg 57]

Transfer Count  

The Transfer Count field is a 32-bit field that is loaded into the Transfer Count register or Indirect List Count register (see pages 47 and 40). The register loaded is determined by the Indirect List 1 field in Enable Word 1.

NOTE: A transfer count of 0 is not supported and results in a control-block error condition.

IMAGE Transfer Count Field [pg 57]

Indirect Lists  

The indirect list is a data structure set up in memory as a contiguous table that is aligned on a doubleword boundary. Each eniry in the table consists of two doubleword fields (the minimum indirect list is one entry of eight bytes).

The address of the first entry in the indirect list and the number of bytes in the indirect list are specified in the Address 2 and Transfer Count fields of the control block.

NOTE: if the address of the indirect list is not aligned on a doubleword boundary or the count is not a multiple of 8 greater than 0, a control-block error occurs.

The format of the indirect list is shown in the following.

Figure 13. Indirect List Structure  
IMAGE Figure 13 [pg 58]

Each entry consists of two doubleword fields.

The first field is the 32-bit Address 2 field that points to a contiguous block in memory that is used as the source or destination for the DMA transfer. This field is loaded into the Memory Address register during the fetch operation for this indirect-list entry.

The second field is the 32-bit Transfer Count field that specifies the number of bytes in the memory block. This field is loaded into the Transfer Count register during the fetch operation for this indirect-list entry.

NOTE: A count of 0 is not supported and results in a control-block error.

31            0
Address 2
Transfer Count

Operations  

In the SCB interface, the DMA controller handles two types of operations, DMA operations and SCB-fetch operations.

DMA Operations  

The DMA operation to be performed is determined by the values loaded into the DMA Mode register, and determines how certain registers are used. The following describes how each of the registers is used for each type of operation.

Arbitration Level Register: A virtual arbitration level capability is provided for each DMA channel.

DMA Mask Register: The Mask field is automatically set to 0 (DMA channel enabled) when a control block is enqueued with the Write Attention command. The Mask field is set to 1 by the DMA controller when the DMA operation is completed.

Transfer Count Register: When the control block is fetched, the DMA controlier loads the Transfer Count register. This register keeps count of the number of bytes to be transferred for that part of the DMA operation.

For operations that do not involve an indirect list (nonchained operations), the register is loaded with the value in the Transfer Count field in the control block. The DMA operation is completed when the Transfer Count register reaches 0 and no bytes remain in the Data Holding register.

For operations that do involve an indirect list (data-chain operations), each fetch from the indirect list loads the Transfer Count register with the value in the Transfer Count field for that entry. The DMA operation ts completed when the Indirect List Count and the Transfer Count registers reach 0 and no bytes remain in the Data Holding register.

Memory Verify Operation  

The memory-verify operation reads data from a memory source and discards the data without writing the data. The operation begins when the arbitrating device is granted control of the system channel, if the DMA channel is enabled.

DMA Mode Register: The DMA controller loads the individual fields of the DMA Mode register with values based on the Command word that is read when the control block is fetched. The following is the contents of the DMA Mode register for a memory-verify operation.

IMAGE DMA Mode Register [pg 61]

I/O-Memory Address Register: This register is loaded with the contents of the Address 1 field when the control block is fetched. This register is not used for memory-verify operation.

Memory Address Register: For nonchained operations, this register is loaded with the value in the Address 2 fieid when the control block is fetched. For data-chained operations, each fetch from the indirect list loads this register with the value in the Address 2 field for that entry.

Memory-to-I/O Transfer Operation  

The memory-to-I/O operation reads data from a location in memory and writes the data to an I/O or DMA device. The operation begins when the arbitrating device is granted control of the system channel, if the DMA channel is enabled.

DMA Mode Register: The DMA controller loads the individual fields of the DMA Mode register with values based on the Command word that is read when the control block is fetched. The following is the contents of the DMA Mode register for a memory-to-I/O transfer.

IMAGE DMA Mode Register [pg 61]

I/O-Memory Address Register: This register is loaded with the contents of the Address 1 field when the control block is fetched.

Memory Address Register: For nonchained operations, this register is loaded with the contents of the Address 2 field. For data-chained operations, each fetch from the indirect list loads this register with the contents of the Address 2 field for that entry.

I/O-to-Memory Transfer Operation  

The I/O-to-memory operation reads data from an I/O or DMA device and writes the data to a location in memory. The operation begins when the arbitrating device is granted control of the system channel, if the DMA channel is enabled.

DMA Mode Register: The DMA controller loads the individual fields of the DMA Mode register with values based on the Command word that is read when the control block is fetched. The following is the contents of the DMA Mode register for a I/O-to-memory transfer.

IMAGE DMA Mode Register [pg 62]

I/O-Memory Address Register: This register is |oaded with the contents of the Address 1 field when the control block is fetched.

Memory Address Register: For nonchained operations, this register is loaded with the value in the Address 2 field when the control block is fetched. For data-chained operations, each fetch from the indirect list loads this register with the value in the Address 2 field for that entry.

SCB Fetch Operations 

The Locate mode in the SCB architecture defines a control structure that allows the system master to indirectly deliver OMA-transfer requests to the DMA controller using contro! blocks and indirect lists. The DMA controiler contains an SCB sequencer, which fetches the control-block and indirect-list information from memory and stores the data in the appropriate DMA transfer registers. The following describes how the SCB sequencer uses the SCB control registers during the control-block fetch operation and subsequent indirect-list fetch operations.

Control Block Fetch Operation 

A control-block fetch operation for an individual DMA channel is performed when the corresponding channel is granted control of the system channel. The control block is fetched at the beginning of the grant cycle before the DMA operation is started.

During a control-block fetch operation, the SCB sequencer reads the 16-byte control block from memory. The SCB sequencer interprets the various fields and uses the information to initialize the appropriate registers for the corresponding DMA channel.

* The Command word is used to initialize the DMA Mode register and to detect the type of control block.
* The Enable Word 1 field identifies whether or not the operation involves data chaining. If the data chaining is being used, the SCB sequencer enqueues a indirect-list-pending request for that DMA channel.
* The Address 1 field is used to initialize the I/O-Memory Address register.
* The Address 2 field is used to initialize the Memory Address register for nonchained operations and is used to initialize the indirect List Address register for data-chained operations.
* The Transfer Count field is used to initialize the Transfer Count register for nonchained operations and is used to intialize the Indirect List Count register for data-chained operations.

Control Block Address Register: This register is loaded by the system master before the control block is enqueued (Write Attention command with request hex 03). After the controi block is enqueued, this register must not be altered until the transfer has been completed (as indicated by the corresponding fieid returned by the Read DMA Busy command). Writing to this register while the DMA channel is busy can cause unpedictable results.

Attention Register: Because DMA operations and system master I/O operations to the DMA controller are mutually exclusive, the SCB sequencer interprets the attention request as it is written to the Attention register. The SCB sequencer sets the Busy field in the Command Busy/Status register to 7, services the Attention register, and resets the Busy field to 0 during a single I/O operation. Therefore, unless the Busy field was set to 1 because of an error, the Busy field is always 0 after the Write Attention command.

When a request code 03 is decoded, the SCB sequencer sets the DMA Mask field to 0 and internally enqueues a SCB-pending request for that DMA channel. The DMA controller allows all eight DMA channeis to have SCB operations pending. The SCB-pending request is cleared when the control block is fetched for that DMA channel or after a Reset DMA Controller or Reset DMA Channel command (see pages 64 and 64).

Indirect List Fetch Operation  

If data chaining is being used, an indirect-list fetch operation is performed immediately after the control-block fetch operation and before the DMA operation is started. During a single system grant cycle, the contro! block is fetched, the first entry in the indirect is fetched, and at least one DMA-transfer cycle occurs. If the indirect list contains multiple entries, additional indirect-list fetch operations are performed. The next entry is fetched immediately after the Transfer Count register goes to 0 and before the DMA controller releases the system channel.

Indirect List Address Register: During data-chained operations, the SCB sequencer uses this register to point to the memory location from which to fetch the next entry in the indirect list. After fetching the entry, the vatue in this register is increased by 8 to point to the next entry in the indirect list.

Indirect List Count Register: During data-chained operations, the SCB sequencer uses this register to count the number of bytes remaining in the indirect list. After fetching the entry, the value in this register is decreased by 8. When the value reaches 0, the SCB sequencer resets the indirect-list-pending request to indicate that no additional fetch operations are required. The Terminai Count field and the ‘terminal count’ signal are disabled until the indirect-list-pending request is reset (see “DMA Status Register” on page 43).

Error Processing  

The DMA controller can detect certain errors that occur as a result of sofware or hardware errors. Aithough the DMA controller is a master, it normally relies on the DMA slave to compete for the system channel and to interrupt the system master. The DMA controller cannot directly notify the DMA slave that an error has been detected. Because the state of the DMA slave is undefined when the DMA operation is haited unexpectedly, the DMA controller relies on the central arbitration control point to force the DMA slave off the system channel and interrupt the system master.

Command Busy/Status Register: The Reject and Busy fields are both set to 1 when SCB-related error is detected.

Subsystem Control Register: This register is used to reset the Reject and Busy fields in the Command Busy/Status register.

Error Conditions  

The DMA controller reports the following conditions as errors when detected.

* The control block address is not aligned on a doubleword boundary.
* The Architected field in the Command word is 1.
* The Transfer Count field in a controt block or indirect list is 0.
* For data-chained operations, the Address 2 field (indirect-list address) is not aligned on a doubleword boundary, or the Transfer Count field (indirect-list count) is not a multiple of 8.

In addition, if the Extend Register field in the DMA Mode register is 0 during an SCB-related transfer operation, an error is reported. This field is set to 1 by the SCB sequencer and is checked at the beginning of each grant cycle. A value of 0 indicates that a Write DMA Mode command was issued before the current DMA operation has been completed (see “SCB Operation Programming Model” on page 76).

Error-Terminated DMA Operation  

When an error condition is detected, the DMA controller uses the following procedures in terminating the DMA operation.

* The DMA controller immediately stops all activity for the current DMA channel and sets the corresponding field in the DMA Mask register to 1.
* The Reject and Busy fields in the Command Busy/Status register are set to 1.
* A bus-timeout request is sent to the central-arbitration control point (CACP).
* After the CACP generates a bus timeout, the DMA controller resets the DMA channel that was active at the time the error was detected (see “DMA Controller Resets” on page 7 for information on registers effected by the reset operation).

Error Recovery  

The following procedure is used to recover from a error detected by the DMA controller.

1. Read the Arbitration register (hex 0090) to verify that a bus timeout has occurred and to identify the arbitration level. (Bit 5 is 1 if a timeout has occurred, and bits 3-0 are the arbitration level.)
2. Read the Command Busy/Status register to determine whether the error was detected by the DMA controller (the Reject field is 1).
3. If the DMA controller caused the error, reset the Command Busy/Status register by writing hex 20 to the Subsystem Control register, and take the appropriate actions to restore the state of the DMA slave involved.
4. Set bit 6 to 0 in the Arbitration register to reset the timeout condition.
5. lf required, the DMA controller registers can be read to determine the cause of the error and the channel status at the time of the error.

Commands  

These commands are used to modify the state of the DMA controller or to return information on the state of the DMA controller. There are two categories of commands through the Function and Extended Function registers:

* Immediate commands
* Execute commands

The function-register commands are I/O operations to the Function and Extended Function registers (at address hex 0018 and 0019). The immediate commands are those functions selected through the Function and Extended Function registers that directly cause the DMA channel or DMA controiler to perform some action. Execute commands are those functions selected through the Function and Extended Function registers that are performed when the Execute Function port (at hex 001A) is accessed.

Figure 14. SCB-interface Commands
Extended Function;Function;Command;Type
;0;Read I/O-memory address;Execute
;1;Read or write control-block address;Execute
;3;Read memory address;Execute
;5;Read transfer count;Execute
;6;Read DMA status;Execute
;7;Read DMA mode;Execute
;8;Read or write arbitration level;Execute
;9;Set DMA mask;Immediate
;A;Reset DMA mask;Immediate
;D;Reset DMA controller;Immediate
00;F;Read DMA busy;Execute
02;F;Restore FIFO data;Execute
03;F;Read FIFO byte count;Execute
0B;F;Read indirect list address;Execute
0C;F;Read indirect list count;Execute
0D;F;Reset DMA channel;Immediate

NOTE: Any values not shown are reserved.

Function Register Commands  

The Function and Extended Function registers are accessed through I/O addresses hex 0018 and 0019 in two single-byte operations.

Read or Write Function  

The read command returns the contents of the Function register. The write command loads the transferred data byte into the register and clears the byte pointer.

The read command does not clear the byte pointer.

IMAGE Function Register [pg 68]

Read or Write Extended Function  

The read command returns the contents of the Extended Function register. The write command loads the transferred data byte into the Extended Function register.

The byte pointer is cleared.

IMAGE Extended Extension Register [pg 68]

Immediate Commands 

For these commands, writing to the Extended Function register causes the operation to be performed. The Select field specifies the DMA channel. These commands are performed immediately and do not require additional I/O accesses to the Execute Function port. The immediate commands are:

* Set DMA Mask
* Reset DMA Mask
* Reset DMA Controller
* Reset DMA Channel

Set DMA Mask  

This command sets the Mask field to 1 for the specified DMA channel. Setting the mask field to 1 disables the DMA channel. The DMA channel is specified in the Select field.

The byte pointer is cleared.

IMAGE Extended Function Set DMA Mask [pg 69]

NOTE: This command is not required for DMA operations.

Reset DMA Mask  

This command sets the Mask field to 0 for the specified DMA channel. Setting this field to 0 enables the DMA channel. The DMA channel is specified in the Select field.

The byte pointer is cleared.

IMAGE Extended Function Reset DMA Mask [pg 69]

NOTE: This command is not required for DMA operations.

Reset DMA Controller  

When it receives the command, the DMA controller:

* Terminates all transfer operations for all DMA channels
* Clears the byte pointer (set to binary 00)
* Sets the Attention register to hex 00
* Sets the Command Busy/Status register to hex 00
* Sets the DMA Status register to hex 00
* Sets the DMA Mask register to hex FF (all channels disabled)

The Select field does not affect this command and should be set to 0.

IMAGE Reset DMA Controller [pg 70]

Reset DMA Channel  

This command resets only those fields and operations associated with the specified DMA channel. A reset of the DMA channel:

* Terminates all transfer operations for the specified channel
* Clears the byte pointer (set to binary 00)
* Sets the Mask field to 1 (disabled)
* Sets the DMA Request field and Terminal! Count field to 0
* Sets the Attention register to hex 00
* Sets the Command Busy/Status register to hex 00

The DMA channel is specified in the Select field.

IMAGE Reset DMA Channel [pg 70]

Execute Commands  

These commands are issued in two parts. First, the Write Function or Write Extended Function command selects the function to perform and the specific register to access. Then, the Execute Function port (hex 001A) is accessed to complete the command. The number of accesses is determined by the number of bytes in the register.

When accessing multiple-byte registers, the byte pointer determines which byte in the register is accessed. The Write Function and Write Extended Function commands reset the byte pointer to point to byte 0 (bits 7-0).

Read I/O-Memory Address  

The read command returns the contents of the I/O-Memory Address register in byte increments. The DMA channel is specified in the Select field.

IMAGE Read I/O Memory Address [pg 71]

Read Memory Address  

This command returns the contents of the Memory Address register in byte increments. The DMA channel is specified in the Select field.

IMAGE Read Memory Address Register [pg 72]

Read Transfer Count  

This command returns the contents of the Transfer Count register in byte increments. The DMA channel is specified in the Select field.

IMAGE Read Transfer Count Register [pg 73]

Read DMA Status  

This command returns each byte of the DMA Status register and clears that byte of the DMA Status register (the byte is set to hex 00).

The Select field does not affect this command.

IMAGE Read DMA Status [pg 73]

Read DMA Mode  

This command returns the contents of the DMA Mode register in byte increments. The DMA channel is specified in the Select field.

IMAGE Read DMA Mode [pg 74]

Read or Write Arbitration Level  

The read command returns the contents of the Arbitration Level register. The write command !oads the transferred data byte into the Arbitration Level register.

The DMA channel is specified in the Select field.

IMAGE R/W ARB Level Register [pg 75]

Read DMA Busy  

This command returns the inverse of the contents of the DMA Mask register. Each bit in the returned data byte indicates whether a DMA channel has an operation pending. If the bit is 0, the corresponding DMA channel does not have an operation pending (it is not busy); if the bit is 1, the channel has not completed the last operation (is busy).

The Select field has no effect on this command and should be set to 0.

IMAGE Read DMA Busy [pg 75]

Restore FIFO Data  

DMA controllers that do not implement a FIFO buffer must ensure that this command is treated as a no-op command. (For information on FIFO implementations, see Appendix B, “FIFO” on page 79.)

NOTE: This command must be performed before attempting to read the FIFO Byte Count register.

IMAGE Restore FIFO Data

Read FIFO Byte Count  

DMA controllers that do not implement a FIFO buffer must ensure that this command returns a hex 00. (For information on FIFO implementations, see Appendix B, “FIFO” on page 79.)

NOTE: The Restore FIFO Data command must be performed before attempting to read the FIFO byte count.

IMAGE Read FIFO Byte Count [pg 77]

Read or Write Control-Block Address  

The read command returns the contents of the Control-Block Address register in byte increments. The write command loads the transferred data bytes into the appropriate bytes of the Control-Block Address register. The DMA channel is specified in the Select field.

NOTE: When an indirect list is betng used, the data returned by the read command is vatid only if the corresponding DMA Request field is 0 (data has not been transferred). Otherwise, the address returned is always valid.

IMAGE R/W Control Block Address [pg 78]

Read Indirect List Address  

This command returns the contents of the Indirect List Address register in byte increments. The DMA channel is specified in the Select field.

NOTE: The data returned by this command is valid only if the corresponding DMA Request field is 1.

IMAGE Read Indirect List Address [pg 79]

Read Indirect List Count  

This command returns the contents of the Indirect List Count register in byte increments. The DMA channel is specified in the Select field.

IMAGE Read Indirect List Count Register [pg 80]

Write Attention Code  

This command loads the transferred data byte into the Attention register. The DMA channel is specified in the Select field.

IMAGE Read Attention Code [pg 81]

Write Subsystem Control  

This command clears the Busy and Reject fields in the Command Busy/Status register.

IMAGE Write Subsystem Control [pg 81]

Read Command Busy/Status  

This command returns the contents of the Command Busy/Status register.

IMAGE Read Command Busy/Status Register

SCB Operation Programming Model  

Each of the eight DMA channels can be programmed independently and can operate concurrently. The DMA controller accepts commands only from the system master and accepts commands to a DMA channel regardless of whether the channel is transferring data or not.

Initialization  

A form of the Locate mode is used to deliver DMA transfer requests to the DMA controller. Although the actual DMA transfer is defined using the control block, the system master uses commands to check the status, to load the operational control registers, and to deliver the SCB request. The following is the procedure for starting a DMA operation using the SCB interface.

1. Set up the control block and the indirect list in memory.
2. Issue the Read DMA Busy command to ensure that the DMA channel is not busy with a previous transfer. If it is busy, wait until the current transfer is completed or terminated.
3. issue the Read Command Busy/Status command to ensure that the Attention register is not busy.
4. Load the Contro!l-Block Address register with the address of the contro! block.
5. Load the Attention register with request code 3 and the DMA channel number.
6. Program the DMA slave to compete for the system channel.

When the arbitration level is granted control of the system channel, the contro! block is fetched, the DMA transfer registers are initialized, and the DMA operation is started.

Termination  

The DMA controller does not require additional steps if the DMA channel operation is allowed to reach terminal count. However, if a DMA channel operation is terminated before terminal count is reached, a Reset DMA Channel command must be issued (see page 64). This command clears all remaining operations enqueued for the specified DMA channel, Other actions can cause subsequent operations using the same DMA channel to have unpredictable results.