9-K and XPOS
US5446869
Configuration and RAM/ROM control of PCI extension card
residing on MCA adapter card My apologies, this started as a SIMMple
documenting the
HITR, 1st Ed. (May 1988) (625 pages)
HITR - Architectures, 1st Ed. (Oct 1990)
SA23-2647-00 RS/6K Hardware Tech Ref - MC Architecture, 1st Ed., 1990
“PCI Specification Revision 2.0-Review Draft Mar. 9, 1993” published by the PCI Special Interest Group, Hillsboro, Oreg.
Table 1 Address space used for POS operations
| ADDRESS | FUNCTION |
| XXX0h | POS Register 0 - Adapter ID Byte (low byte) |
| XXX1h | POS Register 1 - Adapter ID Byte (high byte) |
| XXX2h | POS Register 2 - Option Select Data Byte 1 |
| (Bit 0 is designated as Card Enable) | |
| XXX3h | POS Register 3 - Option Select Data Byte 2 |
| XXX4h | POS Register 4 - Option Select Data Byte 3 |
| XXX5h | POS Register 5 - Option Select Data Byte 4 |
| (Bit 7 is designated as channel check) | |
| (Bit 6 is designated as channel-check-status indicator) | |
| XXX6h | POS Register 6 - Subaddress Extension (low byte) |
| XXX7h | POS Register 7 - Subaddress Extension (high byte) |
Bridge Chip Block Diagram
XPOS registers 10h-13h "PCI Device Configuration registers
10h Bridge Enable register
Bit 1 (the “Placement bit') is read only and identifies whether the adapter
circuitry 16 resides on a local PCI bus on the planar of a PC (not shown) (bit 1 =0) or on the adapter card 14 (bit 1=1). Bit 1 also controls the validity of all other bits
in the Bridge Enable register, such that when the Placement bit is 0, the remaining bits of the Bridge Enable register are "don't cares,” because the daughter card 20
is connected to a local PCI bus (not shown) on the planar of a PC. Otherwise, the remaining bits must be set to control the functions of the bridge 17 with respect
to the daughter card 20. The condition of the Placement bit (i.e., 0 or 1) is determined by a bit in a configuration register in the host 10, which indicates whether the daughter card 20 resides on the adapter card 14 or on the planar.
Bit 2 (the "Decode bit”), identifies whether subtractive (bit 2=0) or subtractive/positive (bit 2=1) address decoding will be supported by the PCI interface 200. Positive decoding is faster, as each PCI device on the PCIbus 18, such as the daughter card 20, will be looking for addresses in the address range(s) assigned to it. Subtractive decoding can be implemented only by one device on the bus 18, in this case, the daughter card 20, because it accepts all accesses not positively decoded by some other agent.
Subtractive decoding is slower because a device must give all other bus agents a "right of first refusal” with respect to each access.
When Decode is = 1, the daughter card supports subtractive decoding, which will allow all other devices (not shown) on the PCI bus 18 to respond with a DEVSEL# signal before responding. If no other device asserts the DEVSEL# line within three PCI clocks, the bridge 17 will drive the line active on the fourth clock, based on the assumption that a PCI bus master (not shown) is attempting to transfer data to or
from the system bus 12. If the adapter circuitry 16 is selected, a positive decoding will be used, in which case the adapter circuitry 16 will assert DEVSEL# within
three PCI clocks after it decodes an address which falls within the address range(s) assigned to it.
If Decode is = 0 or if the Placement bit is set to 1, only positive decodes will be supported. Of the remaining Bridge Enable register bits 3-7, bits 3-6 are reserved for use other than in connection with the present invention and bit 7 is unused.
11h is "PCI Device ID register", which is used to identify which PCI device (not shown) on the daughter card 20 is being selected during a configuration cycle. Because the CDSETUP signal of the MCA bus can only be passed as an IDSEL
signal to a single device on the PCI interface 200, the contents of the Device ID register are used to index the selected device. A five bit value stored in bits 4-0 of the PCI Device ID register, when decoded by the decoder 216, will cause one of the PCI bus AD(31-8) lines, each of which are connected to a single PCI device on the daughter card 20, to be driven high. This active high line is used in connection with the CDSETUP/IDSEL signal to select the one of the PCI devices to be configured. For example, if bits 4-0 of the PCI Device ID register are 01100b, the AD(20) line would be driven high and the device attached thereto would be selected.
12h is "PCI Configuration Address register", which is used in conjunction with
the PCI Device ID register to access a byte of PCI configuration data of the selected PCI device (as indicated by the contents of the Device ID register) during
a configuration cycle. Bits 7-0 of the PCI Configuration Address Register are used as an index to one of the 256 bytes of configuration data of the selected device to be accessed during a configuration cycle. A map of the PCI configuration data space is shown below in Table II:
TABLE 2: PCI configuration data space
| BYTE(S) | DESCRIPTION | ACCESS TYPE |
| 0-1 | Vendor Identification | Read Only |
| 2-3 | Device Identification | Read Only |
| 4-5 | Command | Read/Write |
| 6-7 | Status | Read/Write |
| 8 | Revision D | Read Only |
| 9-Bh | Class Code | Read Only |
| Ch | Cache Line Size | Read/Write |
| Dh | Latency Timer | Read/Write |
| Eh | Header Type | Read Only |
| Fh | Built In Self Test | Read/Write |
| 10-27h | Base Address Registers | Read/Write |
| 28h-2Fh | Reserved | - |
| 30h-33h | Expansion ROM Base Address | Read/Write |
| 34h-37h | Reserved | - |
| 38h-3B | Reserved | - |
| 3Ch | Interrupt Line | Read Only |
| 3Dh | Interrupt Pin | Read Only |
| 3Eh | Min_GNT | Read Only |
| 3Fh | Max_LAT | Read Only |
| 40h-FF | Device Specific | - |
13h is “PCI Configuration Data.” When the XPOS decoder 210 decodes an access
to XPOS register 13h, a PCI Configuration Data Select signal is transmitted to the PCI bus controller 214 via a line 220. Responsive to receipt of the signal on th line
220, the controller 214 transmits control signals to the PCI interface 200 to cause the interface 200 to through put the data from the system bus 12 onto the PCI bus 18. In this manner, data may be written to the selected PCI configuration byte address (as specified in the PCI Configuration Address register) of the selected PCI device (as specified in the PCI Device ID register) via XPOS register 13h.
14h is "Bridge RAM Aperture Size" register, which is used to set the limitations for a system bus 12 to daughter card 20 memory access. The state of bit 0 determines whether the RAM aperture is disabled (bit 0=0) or enabled (bit 0 = 1),
depending on whether the daughter card 20 is present on the adapter card 14 and if so, whether the daughter card 20 includes RAM. When the RAM aperture is
enabled (bit 0 =1), bits 4-1 are used to store, in binary form, a decimal value X for indicating an amount of memory that the daughter card 20 has available, wherein the amount of available memory, in kilobytes, is equal to 2(X+2). For example, if bits 4-1 are 1010b (X=10), the amount of available memory would be equal to 2(10+2) KB, or 4,096 KB.
15h, 16h and 17h are the "Bridge RAM Aperture Address" register, which
contains a 24-bit address comprising the starting address of the daughter card 20 memory based on an 8 KB boundary. During MCA memory cycle decodes, the
PCI bus controller 214 will use the values stored in the Bridge RAM Aperture Size register and the Bridge RAM Aperture Address register to determine whether the on-board RAM (not shown) of the daughter card 20 is being accessed. A value stored in XPOS register 15h comprises the most significant byte (MSB) and a value stored in XPOS register 17h comprises the least significant byte (LSB) of the Bridge RAM Aperture Address register. Because the starting location of the daughter card RAM aperture is based on an 8 KB boundary, bits 4-0 of the Bridge RAM Aperture Address register, i.e., bits 4-0 of XPOS register 17h, are “don’t cares, as the states of these bits are not used in making the comparison.
18h is the "Bridge ROM Aperture Address" register, which is used to indicate the
location of any ROM space of the daughter card 20. The daughter card is allowed only 2 KB of ROM area, and an encoded value stored in bits 7-1 of this register
designates the location of this 2 KB area. Bit 0 is used to disable (bit 0=0) or enable (bit 0=1) the ROM aperture, depending on whether the daughter card includes ROM. The value stored in the Bridge ROM Aperture address register is encoded as shown in Table III below:
Table 3: Bridge ROM Aperture Address
| ENCODED VALUE | ROM APERTURE |
| 00h | 000C0000h-000C07FFh |
| 01h | 000C0800h-000C0FFFh |
| 02h | 000C1000h-000C17FFh |
| " | " |
| " | " |
| " | " |
| 3Dh | 000DE800h-000DEFFFh |
| 3Eh | 000DF000h-000DF7FFh |
| 3Fh | 000DF800h-000DFFFFh |
19h is the "Memory Manager Control" register
Bits 1-0 are used to set the data flow mode of the bridge 17. When the data flow mode is set to RAM or ROM, the bridge 17 provides the data for the ROM signature (offsets 00h, 01h and 02h). Offsets 00h and 01h are hard coded to 55h and AAh, respectively.
19h, Data Flow Mode (bits 1-0)
1-0=00h Passthru, address from MCA passes through bridge to PCI interface, and onto PCI bus.
1-0=01h RAM
1-0=10b ROM
The data for offset 02h is provided by Memory Manager Data register, which will contain 04h or 10h, depending on whether a 2 KB or 8KB aperture has been allocated to the daughter card 20, respectively.
Bits 7-2 are not used.
XPOS registers 14h-1Ah "PCI Memory Access Control registers"
HITR - Architectures, 1st Ed. (Oct 1990)
Channel Check Field Page 112
The Channel Check field is a one-bit, read/write field that indicates the adapter has driven -CHCK active; it is bit 7 of POS Register 5. The adapter sets this field to 0 to indicate it has an exception condition, and the system master resets this field to 1 to reset the adapter after handling the error condition. If the adapter has driven -CHCK active, it must set this field to 0 except for address parity exceptions. If the
system master resets this field to 1 and the adapter is still driving -CHCK active, the adapter must drive -CHCK inactive.
NOTE: If this field is set to 0 during a setup cycle, the adapter should not drive -CHCK active.
bit 7 = 0, exception condition
bit 7 = 1, no exception condition
Auto-incrementing Enable Field Page 113
The Auto Incrementing Enable field is a one-bit, read/write field that enables or disables the automatic incrementing of POS Registers 6 and 7. The default state for this field is disable, which causes the adapter to not perform auto-incrementing. When enabled, it causes POS Registers 6 and 7 to automatically increment for each access to POS Register 3 or 4 (see “POS Subaddress Extension Field” on
page 108).
Channel Check Status Indicator Field Page 114
The Channel Check Status Indicator field is a one-bit, read-only field that indicates if channel-check status is available; it is bit 6 of POS Register 5. The default state of this field is 1. This field is required if the Channel Check field is supported by the adapter.
bit 6 = 1, channel-check condition status is not available.
bit 6 = 0 and Channel Check field (bit 7) is 0, POS Registers 6 and 7 contain the channel-check status or a pointer to the status.
POS Subaddress Extension Field Page 116-119
The POS Subaddress Extension field is an optional, two-byte field that provides a method to extend the POS register space. It is contained in POS Registers 6 and 7 and is used as an index for all setup-cycle accesses to POS Registers 3 and 4. This field allows the subaddressing of up to 128KB of additional information for each adapter.
The POS extension is an extension to POS Registers 3 and 4 and Is made up of two one-byte registers. An index of hex 0000 results in setup cycles accessing POS Register 3 and 4. All adapters supporting the POS extension must set the index to hex 0000 when CHRESET is driven active. The default value for this field is hex 0000.
Adapters supporting POS extension can use POS Registers 6 and 7 as an index register that is automatically incremented for each access to POS Register 3 or 4. Adapters supporting this feature use the Auto-Incrementing field to enable the feature. NOTE: Auto-Increment field is free-form, no set location.
When bits 6 and 7 in POS Register 5 are set to 0, reading POS Registers 6 and 7 will return the channel-check-status information. This information can be status or a pointer to the status.
SA23-2647-00 RS/6K Hardware Tech Ref - MC Architecture, Pages 86-89
The following is an example of how subaddressing could be used to store or access data in the POS extension.
* POS Register 6 is set to hex 01
* POS Register 7 is set to hex 00
What? Maybe POS 5, bit 6 is 01, POS 5, bit 7 is 0 ?
* Access to the POS extension is through POS Register 4
* POS-extension data is in consecutive locations
* Extended POS addressing starts at hex 0001, unless specified by the ADF.
NOTE: The size of POS-extension info that is supported is system dependent.
NOTE: POS 5 bit 7,6 combinations
0,0 - Exception, channel-check status or a pointer to the status in POS 6 / 7
0,1 - Exception, channel-check status NOT available [XPOS available]
1,0 - No exception, channel-check status ? Reserved ?
1,1 - No exception, channel-check status NOT available ? Reserved ?
SUBADDRESSING EXTENSION MCAH, pgs 172-174
Two more 8-bit registers at 0106(hex) and 0107(hex) can serve either as the POS subaddress extension field or status information field or both. The latter is used in conjunction with the channel check and channel check status fields to identify channel check errors. These registers may be used to store error codes, or they can serve as pointers, telling the host computer where the error codes are actually located. The POS subaddress extension field gives the board maker additional space for configuration information and priority communications between the expansion board and computer host, as discussed below.
SUBADDRESSING EXTENSION
The few bytes of data that are stored in registers directly addressable by the POS system can hardly hold all the configuration information that designers might want to maintain for elaborate or esoteric expansion boards. Conditional and optional Micro Channel features already take up most of the storage space available in the basic POS registers.
To sidestep this storage shortage and accommodate a nearly unlimited range of configuration options, the Micro Channel allows for subaddressing through the POS registers. That is, the two registers at card-specific input/output ports 103(hex) and 104(hex) provide a portal through which a large block of additional configuration memory can be accessed. The current Micro Channel specifications allow for a maximum 128 kilobytes (less the first 2 bytes when 6, 7 = 0) of subaddressable configuration memory. ... Registers 106(hex) and 107(hex) keep track of which of the 128K possible bytes show through the portal at registers 103(hex) and 104(hex). In effect, registers 106(hex) and 107(hex) hold address information, and 103(hex) and 104(hex) hold the data stored at the indicated address.
NOTE: "maximum 128 kilobytes (less the first 2 bytes when 6, 7 = 0) of subaddressable configuration memory", does this mean POS 6 -AND- POS 7 are set to 0000, along with POS 5 bits 7,6 being set to 0,1 ?
The subaddress-pointer registers located at input/output ports 106(hex) and 107(hex) serve a dual function, storing channel check status information in addition to pointing to subaddressing data. A specially defined bit, called the channel check status indicator field and located at bit six in the register at I/O port 105(hex), shows which of the two functions these registers are performing at any given time. When the Channel Check Status Indicator Field shows a value of a logical zero, it means that registers 106(hex) and 107(hex) provide Channel Check status (or point to the location where this status information is stored). When this bit indicates a logical one, registers 106(hex) and 107(hex) can be used as pointers to subaddressing data.
When a Micro Channel system starts up, registers 106(hex) and 107(hex) are set to their default values of zero, which indicates that registers 103(hex) and 104(hex) are also set to their default condition as if there were no subaddressing. Setting other values in the two pointer registers retrieves the information stored at the corresponding locations and presents it through registers 103(hex) and 104(hex).
Although nothing in the Micro Channel specification restricts the technology that's used to bring this subaddressed configuration memory to life, ordinarily it will consist of nonvolatile (backed up by battery) CMOS chips. Inexpensive nonvolatile RAM modules are typically organized with a serial interface, that is, they output the data they hold sequentially, one byte after another.
The Micro Channel provides a mechanism for quickly obtaining data serially stored in subaddressed configuration memory. The pointer value stored in registers 106(hex) and 107(hex) can be made to automatically increment every time the data registers at 103(hex) and 104(hex) are accessed. This auto-incrementing process steps through all the data contained in subaddressed configuration memory without the need to alternately write at one register then read another.
Whether the data registers auto-increment is determined by a special configuration status bit called the auto-incrementing enable field. When this bit is set at a logical one, auto-incrementing is enabled; a logical zero disables the function. This bit can be located anywhere in any configuration-memory register (that does not conflict with another function) at the discretion of the designer of the expansion board. The board knows which bit it is, and that's all that counts.
The overall effect of the subaddressing extension to the programmable option select system expands the available data available for use during system set up, initial loading of programs, subsystem control block operations, and other Micro Channel functions. The information stored at the subaddress is accessible to both the main system processor and the subsystem. It's like a private mailbox between the system board processor and the expansion board. It's private because it's exclusively under the control of the expansion board and cannot be directly accessed by another board.
In a multiprocessing computer system, each intelligent device in the system (such as a bus master) could use the subaddressed mailbox to receive private control block information or return status blocks from an executive control program. IBM recommends that as many elements as possible in a given system use a similar format for such control blocks in order to simplify the executive control program (for example, see Figure 12.8.)
Using the subaddressing extension offers the advantage that each expansion board needs to add to the system only the memory it needs for its own functions. This memory is isolated from other expansion boards (and hence, other processors) in the system. This independence means that it won't be affected by problems in other parts of the system nor will it need to draw memory away from other processors for its communications or set-up functions. Using the subaddress extension, each expansion board can individually engage in private communications with the system microprocessor without affecting other bus masters or slaves in the system.
The subaddressing extension is not the only way the reach of POS can be extended, however. The Micro Channel design also allows the use of two special set-up files to adjust and initialize expansion board functions in ways that POS by itself cannot handle. These special files are discussed in the next chapter.
HITR, 1st Ed. (May 1988) (625 pages) Page 92-94
Adapter POS Implementation
The following figure shows how an adapter typically implements POS.
All designs must latch the least-significant bit of the device-dependent option-select byte. Bit 7 of POS Register 5 is set to 1 unless -CHCK is active from the adapter. The remaining bits can be implemented as required.
NOTE: Any adapter that POS does not completely initialize should implement a second enable, which is activated by adapter ROM routines or loadable software. The card-disable function (POS Register 2, bit 0) must override a second enable.
The following figure shows the subaddressing extension for memory. The counter registers increment after each least-significant byte of option-select information is written.
