Group 1 POS Register 2 (Hex 0102)
Group 1 POS Register 2 (Hex 0102) When group 1 is in setup mode, this read/write register controls the diskette drive controller and parallel port B. +-----------------------------------------------+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |-----+-----------+-----+-----+-----+-----+-----| | BID | SEL | PP | 1 | 0 | DDE | ENA | +-----------------------------------------------+ NOTE: BID: Disable bidirectional mode SELECT: Parallel port B select PP: Enable parallel port B DDE: Enable diskette drives ENA: Enable system board functions R: Reserved BID The disable-bidirectional-mode fit controls whether parallel port B is configured as a bidirectional parallel port (extended mode) or unidirectional parallel port (sometimes called the compatible mode). When this bit is set to 1, the parallel port is an output-port only. When the bit is set to 0, the parallel port is bidirectional. The default is bidirectional mode. SELECT The parallel-port-select
bits configure parallel port B on the system board.
*** For DMA operations, the addresses are hex 1278-127D. PP The enable-parallel-port bit enables and disables parallel port B on the system board. When this bit and bit 0 are set to 1, parallel port B is enabled. When either bit is set to 0, the parallel port is disabled. DDE The enable-diskette-drives bit enables and disables the diskette drive controller. When this bit and bit 0 are set to 1, the controller is enabled. When either bit is set to 0, the controller is disabled. ENA The enable-system-board-I/O bit provides a single bit to disable I/O controllers on the system board (diskette drive controller, both serial ports, and parallel port B). When this bit is set to 0, all system board functions are disabled. When this bit is set to 1, these functions can be controlled by their respective bits. Note: Disabling the system board
functions does not disable their interrupt request signals. Therefore,
the interrupts must be disabled individually before the device is disabled.
Group 1 POS Register 3 (Hex 0103) This register acts as a data port and is used to access information about memory connectors on the system board (see Memory Connectors). To access the information, write the desired index to address 0103h, then read 0103h. Write +-----------------------------------------------+
Memory Connector
Information
Parity/-ECC
Information
Operator
Panel Information
+-----------------------------------------------+
UA The unattended-power-on-status bit indicates whether the power switch is in the standby mode or the power-on mode. When this bit is 0, the power switch is in the standby mode, and the system was powered-on through the wake-up or kickstart feature. If the bit is 1, the system was powered-on with the power switch. PANEL The panel field is a
4-bit field that identifies the operator panel.
Group 1 POS Register 4 (Hex 0104) This register is used to control the diskette drive arbitration. +-----------------------------------------------+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |-----------+-----+-----+-----------------------| | Reserved | BE | F | ARB | +-----------------------------------------------+ BE: Diskette burst enable F: Diskette fairness enable ARB: Diskette arbitration level BE The burst-enable bit determines
whether the diskette-drive controller performs burst transfers to memory.
Burst transfers reduce the time it takes to transfer data because the controller
transfers a block of data each time it gets control of the system bus.
F The fairness-enable bit determines whether the diskette drive controller uses fairness when arbitrating for control of the system channel. When this bit is set to 1, fairness is enabled for the diskette drive controller. When this bit is set to 0, fairness is disabled. Note: Fairness is disabled during POST and should not be changed. ARB The diskette-drive arbitration-level
bits select the arbitration level used by the diskette drive controller.
The default arbitration value is 2.
Group 1 POS Register 5 (Hex 0105) This register is used to specify the arbitration level for parallel port B. +-----------------------------------------------+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |-----------------------+-----------------------| | Reserved | Arb Level | +-----------------------------------------------+ Arb Level The parallel-port arbitration-level
bits select the arbitration level used by parallel port B.
|