POWER3 Details

• SMP - 2-16 CPUs per node

• 64-bit architecture and address space

• Clock speeds range from 200 - 450 MHz

• There are 4 different types of POWER3 nodes, referred to as Winterhawk-1, Winterhawk-2, Nighthawk-1 and Nighthawk-2, which vary in number of CPUs, clock speeds, etc. A diagram of the 16-CPU Nighthawk-2 node is shown below.

  

• Memory/Cache:
  • L1 Data Cache: 64 KB, 128 byte line, 128-way associative
  • L1 Instruction Cache: 32 KB, 128 byte line, 128-way associative
  • L2 Cache: up to 16 MB, 128 byte line, 8-way associative
  • L2 cache has its own bus - can be accessed simultaneously with main memory
  • Maximum Memory: depends on model - up to 64 GB shared memory for the 16-way NH2 high nodes.

• Separate data and address buses.

• Superscalar CPU - 8 execution units which can operate simultaneously:
  • 2 floating point units
  • 3 fixed point units
  • 2 load/store units
  • Branch unit
  • Condition Register Unit

• I/O & switch bus operates concurrently and independently from memory-cache bus