Intel® Pentium® II Xeon™ (SLOT 2) - CPU Connector

 
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Intel® Pentium® II Xeon™ - PROCESSOR (SLOT 2) Edge Finger Signal (330-pin) Listing

Pin # Pin Name Signal Buffer Type Pin # Pin Name Signal Buffer Type
A1 EMI Connect to VSS B1 PWR_EN[1] Short to PWR_EN[0]
A2 VCC_TAP TAP Supply B2 VCC_CORE CPU Core VCC
A3 EMI Connect to VSS B3 RESERVED_B3 DO NOT CONNECT
A4 VSS Ground B4 TEST_VSS_B4 Pull down to VSS
A5 VTT AGTL+ VTT Supply B5 VCC_CORE CPU Core VCC
A6 VTT AGTL+ VTT Supply B6 VTT AGTL+ VTT Supply
A7 VSS Ground B7 VTT AGTL+ VTT Supply
A8 VSS Ground B8 VCC_CORE CPU Core VCC
A9 SELFSB0 CMOS I/O B9 RESERVED_B9 DO NOT CONNECT
A10 VSS Ground B10 FLUSH# CMOS Input
A11 TEST_VSS_A11 Pull down to VSS B11 VCC_CORE CPU Core VCC
A12 IERR# CMOS Output B12 SMI# CMOS Input
A13 VSS Ground B13 INIT# CMOS Input
A14 A20M# CMOS Input B14 VCC_CORE CPU Core VCC
A15 FERR# CMOS Output B15 STPCLK# CMOS Input
A16 VSS Ground B16 TCK TAP Clock
A17 IGNNE# CMOS Input B17 VCC_CORE CPU Core VCC
A18 TDI TAP Input B18 SLP# CMOS Input
A19 VSS Ground B19 TMS TAP Input
A20 TDO TAP Output B20 VCC_CORE CPU Core VCC
A21 PWRGOOD CMOS Input B21 TRST# TAP Input
A22 VSS Ground B22 RESERVED_B22 DO NOT CONNECT
A23 TEST_VCC_CORE_A23 Pull up to VCC_CORE B23 VCC_CORE CPU Core VCC
A24 THERMTRIP# CMOS Output B24 RESERVED_B24 DO NOT CONNECT
A25 VSS Ground B25 RESERVED_B25 DO NOT CONNECT
A26 RESERVED_A26 DO NOT CONNECT B26 VCC_CORE CPU Core VCC
A27 LINT[0] CMOS Input B27 TEST_VCC_CORE_B27 Pull up to VCC_CORE
A28 VSS Ground B28 LINT[1] CMOS Input
A29 PICD[0] CMOS I/O B29 VCC_CORE CPU Core VCC
A30 PREQ# CMOS Input B30 PICCLK APIC Clock Input
A31 VSS Ground B31 PICD[1] CMOS I/O
A32 BP#[3] AGTL+ I/O B32 VCC_CORE CPU Core VCC
A33 BPM#[0] AGTL+ I/O B33 BP#[2] AGTL+ I/O
A34 VSS Ground B34 RESERVED_B34 DO NOT CONNECT
A35 BINIT# AGTL+ I/O B35 VCC_CORE CPU Core VCC
A36 DEP#[0] AGTL+ I/O B36 PRDY# AGTL+ Output
A37 VSS Ground B37 BPM#[1] AGTL+ I/O
A38 DEP#[1] AGTL+ I/O B38 VCC_CORE CPU Core VCC
A39 DEP#[3] AGTL+ I/O B39 DEP#[2] AGTL+ I/O
A40 VSS Ground B40 DEP#[4] AGTL+ I/O
A41 DEP#[5] AGTL+ I/O B41 VCC_CORE CPU Core VCC
A42 DEP#[6] AGTL+ I/O B42 DEP#[7] AGTL+ I/O
A43 VSS Ground B43 D#[62] AGTL+ I/O
A44 D#[61] AGTL+ I/O B44 VCC_CORE CPU Core VCC
A45 D#[55] AGTL+ I/O B45 D#[58] AGTL+ I/O
A46 VSS Ground B46 D#[63] AGTL+ I/O
A47 D#[60] AGTL+ I/O B47 VCC_CORE CPU Core VCC
A48 D#[53] AGTL+ I/O B48 D#[56] AGTL+ I/O
A49 VSS Ground B49 D#[50] AGTL+ I/O
A50 D#[57] AGTL+ I/O B50 VCC_CORE CPU Core VCC
A51 D#[46] AGTL+ I/O B51 D#[54] AGTL+ I/O
A52 VSS Ground B52 D#[59] AGTL+ I/O
A53 D#[49] AGTL+ I/O B53 VCC_CORE CPU Core VCC
A54 D#[51] AGTL+ I/O B54 D#[48] AGTL+ I/O
A55 VSS Ground B55 D#[52] AGTL+ I/O
A56 RESERVED_A56 DO NOT CONNECT B56 VCC_CORE CPU Core VCC
A57 VSS Ground B57 RESERVED_B57 DO NOT CONNECT
A58 D#[42] AGTL+ I/O B58 VCC_CORE CPU Core VCC
A59 D#[45] AGTL+ I/O B59 D#[41] AGTL+ I/O
A60 VSS Ground B60 D#[47] AGTL+ I/O
A61 D#[39] AGTL+ I/O B61 VCC_CORE CPU Core VCC
A62 TEST_25_A62 Pull up to 2.5 V B62 D#[44] AGTL+ I/O
A63 VSS Ground B63 D#[36] AGTL+ I/O
A64 D#[43] AGTL+ I/O B64 VCC_CORE CPU Core VCC
A65 D#[37] AGTL+ I/O B65 D#[40] AGTL+ I/O
A66 VSS Ground B66 D#[34] AGTL+ I/O
A67 D#[33] AGTL+ I/O B67 VCC_CORE CPU Core VCC
A68 D#[35] AGTL+ I/O B68 D#[38] AGTL+ I/O
A69 VSS Ground B69 D#[32] AGTL+ I/O
A70 D#[31] AGTL+ I/O B70 VCC_CORE CPU Core VCC
A71 D#[30] AGTL+ I/O B71 D#[28] AGTL+ I/O
A72 VSS Ground B72 D#[29] AGTL+ I/O
A73 D#[27] AGTL+ I/O B73 VCC_CORE CPU Core VCC
A74 D#[24] AGTL+ I/O B74 D#[26] AGTL+ I/O
A75 VSS Ground B75 D#[25] AGTL+ I/O
A76 D#[23] AGTL+ I/O B76 VCC_CORE CPU Core VCC
A77 D#[21] AGTL+ I/O B77 D#[22] AGTL+ I/O
A78 VSS Ground B78 D#[19] AGTL+ I/O
A79 D#[16] AGTL+ I/O B79 VCC_CORE CPU Core VCC
A80 D#[13] AGTL+ I/O B80 D#[18] AGTL+ I/O
A81 VSS Ground B81 D#[20] AGTL+ I/O
A82 TEST_VTT_A82 Pull up to VTT B82 VCC_CORE CPU Core VCC
A83 RESERVED_A83 DO NOT CONNECT B83 RESERVED_B83 DO NOT CONNECT
A84 VSS Ground B84 RESERVED_B84 DO NOT CONNECT
A85 D#[11] AGTL+ I/O B85 VCC_CORE CPU Core VCC
A86 D#[10] AGTL+ I/O B86 D#[17] AGTL+ I/O
A87 VSS Ground B87 D#[15] AGTL+ I/O
A88 D#[14] AGTL+ I/O B88 VCC_CORE CPU Core VCC
A89 D#[09] AGTL+ I/O B89 D#[12] AGTL+ I/O
A90 VSS Ground B90 D#[07] AGTL+ I/O
A91 D#[08] AGTL+ I/O B91 VCC_CORE CPU Core VCC
A92 D#[05] AGTL+ I/O B92 D#[06] AGTL+ I/O
A93 VSS Ground B93 D#[04] AGTL+ I/O
A94 D#[03] AGTL+ I/O B94 VCC_CORE CPU Core VCC
A95 D#[01] AGTL+ I/O B95 D#[02] AGTL+ I/O
A96 VSS Ground B96 D#[00] AGTL+ I/O
A97 BCLK System Bus Clock B97 VCC_CORE CPU Core VCC
A98 TEST_ VSS _A98 Pull down to VSS B98 RESET# AGTL+ Input
A99 VSS Ground B99 FRCERR AGTL+ I/O
A100 BERR# AGTL+ I/O B100 VCC_CORE CPU Core VCC
A101 A#[33] AGTL+ I/O B101 A#[35] AGTL+ I/O
A102 VSS Ground B102 A#[32] AGTL+ I/O
A103 A#[34] AGTL+ I/O B103 VCC_CORE CPU Core VCC
A104 A#[30] AGTL+ I/O B104 A#[29] AGTL+ I/O
A105 VSS Ground B105 A#[26] AGTL+ I/O
A106 A#[31] AGTL+ I/O B106 VCC_L2 L2 Cache VCC
A107 A#[27] AGTL+ I/O B107 A#[24] AGTL+ I/O
A108 VSS Ground B108 A#[28] AGTL+ I/O
A109 A#[22] AGTL+ I/O B109 VCC_L2 L2 Cache VCC
A110 A#[23] AGTL+ I/O B110 A#[20] AGTL+ I/O
A111 VSS Ground B111 A#[21] AGTL+ I/O
A112 A#[19] AGTL+ I/O B112 VCC_L2 L2 Cache VCC
A113 A#[18] AGTL+ I/O B113 A#[25] AGTL+ I/O
A114 VSS Ground B114 A#[15] AGTL+ I/O
A115 A#[16] AGTL+ I/O B115 VCC_L2 L2 Cache VCC
A116 A#[13] AGTL+ I/O B116 A#[17] AGTL+ I/O
A117 VSS Ground B117 A#[11] AGTL+ I/O
A118 A#[14] AGTL+ I/O B118 VCC_L2 L2 Cache VCC
A119 VSS Ground B119 A#[12] AGTL+ I/O
A120 A#[10] AGTL+ I/O B120 VCC_L2 L2 Cache VCC
A121 A#[05] AGTL+ I/O B121 A#[08] AGTL+ I/O
A122 VSS Ground B122 A#[07] AGTL+ I/O
A123 A#[09] AGTL+ I/O B123 VCC_L2 L2 Cache VCC
A124 A#[04] AGTL+ I/O B124 A#[03] AGTL+ I/O
A125 VSS Ground B125 A#[06] AGTL+ I/O
A126 RESERVED_A126 DO NOT CONNECT B126 VCC_L2 L2 Cache VCC
A127 BNR# AGTL+ I/O B127 AERR# AGTL+ I/O
A128 VSS Ground B128 REQ#[0] AGTL+ I/O
A129 BPRI# AGTL+ Input B129 VCC_L2 L2 Cache VCC
A130 TRDY# AGTL+ Input B130 REQ#[1] AGTL+ I/O
A131 VSS Ground B131 REQ#[4] AGTL+ I/O
A132 DEFER# AGTL+ Input B132 VCC_L2 L2 Cache VCC
A133 REQ#[2] AGTL+ I/O B133 LOCK# AGTL+ I/O
A134 VSS Ground B134 DRDY# AGTL+ I/O
A135 REQ#[3] AGTL+ I/O B135 VCC_L2 L2 Cache VCC
A136 HITM# AGTL+ I/O B136 RS#[0] AGTL+ Input
A137 VSS Ground B137 HIT# AGTL+ I/O
A138 DBSY# AGTL+ I/O B138 VCC_L2 L2 Cache VCC
A139 RS#[1] AGTL+ Input B139 RS#[2] AGTL+ Input
A140 VSS Ground B140 RP# AGTL+ I/O
A141 BR2# AGTL+ Input B141 VCC_L2 L2 Cache VCC
A142 BR0# AGTL+ I/O B142 BR3# AGTL+ Input
A143 VSS Ground B143 BR1# AGTL+ Input
A144 ADS# AGTL+ I/O B144 VCC_L2 L2 Cache VCC
A145 AP#[0] AGTL+ I/O B145 RSP# AGTL+ Input
A146 VSS Ground B146 AP#[1] AGTL+ I/O
A147 VID_CORE[2] Open or Short to VSS B147 VCC_L2 L2 Cache VCC
A148 VID_CORE[1] Open or Short to VSS B148 WP SMBus Input
A149 VSS Ground B149 VID_CORE[3] Open or Short to VSS
A150 VID_CORE[4] Open or Short to VSS B150 VCC_L2 L2 Cache VCC
A151 SMBALERT# SMBus Alert B151 VID_CORE[0] Open or Short to VSS
A152 VSS Ground B152 VID_L2[0] Open or Short to VSS
A153 VID_L2[2] Open or Short to VSS B153 VCC_L2 L2 Cache VCC
A154 VID_L2[1] Open or Short to VSS B154 VID_L2[4] Open or Short to VSS
A155 VSS Ground B155 VID_L2[3] Open or Short to VSS
A156 VTT AGTL+ VTT Supply B156 VCC_L2 L2 Cache VCC
A157 VTT AGTL+ VTT Supply B157 VTT AGTL+ VTT Supply
A158 VSS Ground B158 VTT AGTL+ VTT Supply
A159 SA2 SMBus Input B159 VCC_L2 L2 Cache VCC
A160 VCC_SM SMBus Supply B160 SMBCLK SMBus Clock
A161 VSS Ground B161 SMBDAT SMBus Data
A162 SA1 SMBus Input B162 VCC_L2 L2 Cache VCC
A163 SA0 SMBus Input B163 RESERVED_B163 DO NOT CONNECT
A164 VSS Ground B164 EMI Connect to VSS
A165 PWR_EN[0] Short to PWR_EN[1] B165 EMI Connect to VSS

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